DIRECTORY Commander, Dragon, DragOpsCross, IFUPLAMainControl, IO, PLAOps; IFUPLAMainControlImpl: CEDAR PROGRAM IMPORTS Commander, IO, PLAOps = BEGIN OPEN IFUPLAMainControl, PLAOps; MainControlPLA: PLAOps.PLA; condEffectNotSig: CondEffect _ FIRST [CondEffect]; condEffectIsSig: CondEffect _ LAST [CondEffect]; pBusFaultNotSig: Dragon.PBusFaults _ FIRST [Dragon.PBusFaults]; pBusFaultIsSig: Dragon.PBusFaults _ LAST [Dragon.PBusFaults]; forceBubble: MainControlOut = [microExcptJmp: bubble, exceptionCode: bubble]; GenMainControlPLA: PROC = { cur, temp: BoolExpr; euStkOverflow: BoolExpr _ And[ BEX[[trapsEnbled2: TRUE]], BEX[[eStkOverflow2: TRUE]] ]; ifuStkOverflow: BoolExpr _ And[ BEX[[trapsEnbled2: TRUE]], BEX[[iStkNearlyFull2: TRUE]], Or[ BEX[[dpFaulted: TRUE]], And[ BEXNot[[dpRejected: TRUE]], Or[ BEX[[push2: TRUE]], BEX[[eStkOverflow2: TRUE]], BEX[[ipFaulted2: TRUE]], And[BEX[[instStarting2: TRUE]], BEX[[rschlWaiting2: TRUE]]], And[ BEX[[euCondition2: TRUE]], BE[ m: [euCondEffect2: condEffectIsSig], d: [euCondEffect2: macroTrap] ] ] ] ] ] ]; interlock: BoolExpr _ And[ Or[ BEX[[stage1Hold: TRUE]], And[ BEX[[dpRejected: TRUE]] ] ], Not[BE[m: [condEffect1: condEffectIsSig], d: [condEffect1: bubble]]] ]; Set[m:[reseting: TRUE], d:[reseting: TRUE], out:[ abortPipe: TRUE, microExcptJmp: resetting, exceptionCode: reset ] ]; cur _ BEXNot[[reseting: TRUE]]; Set[s:cur, m:[protMicroCyc: TRUE], d:[protMicroCyc: TRUE], out:[ microExcptJmp: none, exceptionCode: none ] ]; cur _ And[cur, BEXNot[[protMicroCyc: TRUE]]]; Set[s: And[cur, ifuStkOverflow], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: iStkOFlow ] ]; cur _ And[cur, Not[ifuStkOverflow]]; Set[s:cur, m:[dpFaulted: TRUE], d:[dpFaulted: TRUE], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: dpFault ] ]; cur _ And[cur, BEXNot[[dpFaulted: TRUE]]]; Set[s: And[cur, BEX[[dpRejected: TRUE]], interlock], out: forceBubble ]; cur _ And[cur, BEXNot[[dpRejected: TRUE]]]; temp _ And[cur, BEX[[euCondition2: TRUE]]]; Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: macroTrap], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: cTrap ] ]; Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: macroJump], out:[ abortPipe: TRUE, microExcptJmp: cJump, exceptionCode: cJump ] ]; Set[s:temp, m:[euCondEffect2: condEffectIsSig], d:[euCondEffect2: microJump], out:[ microExcptJmp: microJump ] ]; cur _ And[cur, BEXNot[[euCondition2: TRUE]]]; Set[s: And[cur, euStkOverflow], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: eStkOFlow ] ]; cur _ And[cur, Not[euStkOverflow]]; Set[s: And[cur, interlock], out: forceBubble ]; cur _ And[cur, Not[interlock]]; cur _ And[cur, BEX[[instStarting2: TRUE]] ]; Set[s: And[cur, BEX[[trapsEnbled2: TRUE]]], m:[rschlWaiting2: TRUE], d:[rschlWaiting2: TRUE], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: rschlWait ]]; cur _ And[cur, Or[BEXNot[[rschlWaiting2: TRUE]], BEXNot[[trapsEnbled2: TRUE]]]]; Set[s:cur, m:[ipFaulted2: TRUE], d:[ipFaulted2: TRUE], out:[ abortPipe: TRUE, microExcptJmp: trap, exceptionCode: ipFault ]]; cur _ And[cur, BEXNot[[ipFaulted2: TRUE]]]; }; BE: PROC [m, d: MainControlIn ] RETURNS[ BoolExpr ] = { mRef: REF MainControlIn _ NARROW[MainControlPLA.mask]; dRef: REF MainControlIn _ NARROW[MainControlPLA.data]; mRef^ _ m; dRef^ _ d; RETURN[GetBEForDataMask[MainControlPLA]]}; BEX: PROC [ d: MainControlIn ] RETURNS[ BoolExpr ] = { RETURN[ BE[d,d] ] }; BEXNot: PROC [ d: MainControlIn ] RETURNS[ BoolExpr ] = { RETURN[ BE[d,[]] ] }; Set: PROC [s: BoolExpr _ NIL, m, d: MainControlIn _ [ ], out: MainControlOut] = { res: REF MainControlOut _ NARROW[MainControlPLA.out]; IF s=NIL THEN s _ BE[m,d] ELSE s _ And[s, BE[m,d] ]; res^ _ out; SetOutForBE[MainControlPLA, s]}; GenMainControl: Commander.CommandProc = { filename: IO.ROPE _ DefaultCMDLine[cmd.commandLine, defaultFile]; MainControlPLA _ NewPLA["IFUPLAMainControl.MainControlIn", "IFUPLAMainControl.MainControlOut"]; GenMainControlPLA[]; [ ] _ ConvertTermListToCompleteSum[MainControlPLA.termList, FALSE, FALSE, cmd.out]; [ ] _ FindAMinimalCover[MainControlPLA.termList, 120, cmd.out]; WritePLAFile[filename, cmd.out, MainControlPLA] }; doc: IO.ROPE = "Expects the name of the ttt file"; defaultFile: IO.ROPE = "IFUPLAMainControl.ttt"; Commander.Register[key:"GenMainControl", proc: GenMainControl, doc: doc]; END. hIFUPLAMainControlImpl.mesa Copyright c 1984 by Xerox Corporation. All rights reserved. Last edited by Curry, May 13, 1986 7:46:36 pm PDT McCreight, February 28, 1986 12:03:45 pm PST MainControlProc: PROC[args: MainControlIn] RETURNS[result: MainControlOut]; BEX[[stage1HoldIfReject: TRUE]], Reset Intermediate cycle of protected microinstruction sequence IFU stack overflow Data PBus Fault, pipe stage 3 Reject ALU Condition, pipe stage 2 EU stack overflow, pipe stage 2 Pipe Interlock Reschedule Waiting, pipe stage 2 Instruction Fetch Fault, pipe stage 2 ELSE new unexceptional microinstruction [ ] Ê(˜šœ™Jšœ<™˜DJšœ˜J˜—JšÏb™šœœœ˜1Jšœœ˜Jšœ˜Jšœ˜—Jšœœ˜J˜JšŸ9™9šœœœ˜@Jšœ˜Jšœ˜—Jšœ%œ˜-J˜JšŸ™šœ&˜&Jšœœ˜Jšœ˜Jšœ˜—Jšœ$˜$J™JšŸ™šœœœ˜:Jšœœ˜Jšœ˜Jšœ˜—šœ"œ˜*J˜—JšŸ™Jšœœœ#˜HJšœ#œ˜+J˜JšŸ™Jšœœœ˜+šœS˜SJšœœ˜Jšœ˜Jšœ˜—šœS˜SJšœœ˜Jšœ˜Jšœ˜—šœS˜SJšœ˜—Jšœ%œ˜-J˜JšŸ™šœ%˜%Jšœœ˜Jšœ˜Jšœ˜—Jšœ#˜#J˜JšŸ™Jšœ/˜/Jšœ˜J˜šœœœ˜,J˜—JšŸ ™ š œœœœœ˜cJšœœ˜Jšœ˜Jšœ˜—Jšœ)œœ˜PJ˜JšŸ%™%šœœœ˜