IFUPLAInstrDecodeImpl3.mesa
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, September 10, 1986 10:42:00 pm PDT
Herrmann, August 14, 1985 1:01:48 pm PDT
McCreight, February 4, 1986 9:50:31 am PST
DIRECTORY
DragOpsCross,
IFUPLAInstrDecode,
PLAOps;
IFUPLAInstrDecodeImpl3: CEDAR PROGRAM
IMPORTS IFUPLAInstrDecode EXPORTS IFUPLAInstrDecode =
BEGIN OPEN IFUPLAInstrDecode, PLAOps;
m:   InstrDecodeOut;
GenInstrDecodePLA3: PUBLIC GenInstrDecodePLAProc = {
current ← old;
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dADDB], out:[
aReg: abStackTop,
x2ALitSource: alpha,
cReg: cStackTop,
aluOp: SAdd,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSUBB], out:[
aReg: abStackTop,
x2ALitSource: alpha,
cReg: cStackTop,
aluOp: SSub,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dADDDB], out:[
aReg: abStackTop,
x2ALitSource: alphaBeta,
cReg: cStackTop,
aluOp: SAdd,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSUBDB], out:[
aReg: abStackTop,
x2ALitSource: alphaBeta,
cReg: cStackTop,
aluOp: SSub,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dADDQB], out:[
aReg: abStackTop,
x2ALitSource: alpBetGamDel,
cReg: cStackTop,
aluOp: SAdd,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSUBQB], out:[
aReg: abStackTop,
x2ALitSource: alpBetGamDel,
cReg: cStackTop,
aluOp: SSub,
condSel: OvFl ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSHDL], out:[
aReg:    [ s, offset, minus1 ],
bReg:    [ s, offset, zero ],
popSb:   TRUE,
x2ALitSource: alphaBeta,
cReg:    [s, offset, minus1],
aluOp:   FOP ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSHDR], out:[
aReg:    [ s, offset, zero ],
bReg:    [ s, offset, minus1 ],
popSb:   TRUE,
x2ALitSource: alphaBeta,
cReg:    [s, offset, minus1],
aluOp:   FOP ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSHL], out:[
aReg: [ s, offset, zero ],
bReg: [ cBase, offset, zero ],
x2ALitSource: alphaBeta,
cReg: cStackTop,
aluOp: FOP ]];
Set[s:current, m:[op: InstrTopSig[8]], d:[op: dSHR], out:[
aReg: [ s, offset, zero ],
bReg: [ s, offset, zero ],
x2ALitSource: alphaBeta,
cReg: [ s, offset, zero ],
aluOp: FOP ]];
Comment out Mul and Div for now
instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dSMUL]]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, zero ],  -- Lt ← S=Multiplicand
bReg: [ s, offset, minus1 ], -- MQ ← Rt ← Multiplier
cReg: [ s, offset, minus1 ], -- Product.msw
aluOp: MulLd,
condSel: EZ,    -- IF aluout=Lt=Multiplicand is zero then quit
condEffect0: microJump]]; -- cycle ← microFixedJump if zero
m ← [ -- 1..16
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, minus1 ], -- Product.msw
bReg: [ s, offset, zero ],  -- Multiplicand
cReg: [ s, offset, minus1 ], -- Product.msw mulcandS
aluOp: MulStep ];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 1], out: m]; -- 1
Set[s: instr, m:[state: ByteTopSig[7]], d:[state: 2], out: m]; -- 2.. 3
Set[s: instr, m:[state: ByteTopSig[6]], d:[state: 4], out: m]; -- 4.. 7
Set[s: instr, m:[state: ByteTopSig[5]], d:[state: 8], out: m]; -- 8..15
Set[s: instr, m:[state: ByteTopSig[8]], d:[state:16], out: m]; -- 16
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 17], out:[
nextMacro: get,
pcNext: fromPCBus,
microCycleNext: next,
cReg: [ s, offset, zero ],  -- Product.lsw ← MQ
aluOp: RdMQ ]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: fixedMicroJump], out:[
aReg: constantZero,  -- Product.msw
bReg: constantZero,  -- Multiplicand
cReg: [ s, offset, minus1 ], -- Product.msw ← 0
aluOp: Or ]];
instr ← And[current, BE[m:[op: InstrTopSig[8]], d:[op: dUDIV]]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg: [ s, offset, minus2 ], -- Dividend MSW
bReg: [ s, offset, minus1 ], -- Dividend LSW
cReg: [ s, offset, one ],
aluOp: DivLdDbl]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg:  [ s, offset, one ],  -- Dividend.msw (temp location)
bReg:  [ s, offset, zero ],  -- Divisor
cReg:  [ s, offset, minus1 ], -- Remainder destination
aluOp:  DivCk,
condSel:  DivOvFl,
condEffect0: macroTrap ]];
m ← [ -- 2..32
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg:  [ s, offset, minus1 ], -- Remainder source
bReg:  [ s, offset, zero ],  -- Divisor
cReg:  [ s, offset, minus1 ], -- Remainder destination
aluOp: DivStep ];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 3], out: m]; -- 3
Set[s: instr, m:[state: ByteTopSig[6]], d:[state: 4], out: m]; -- 4.. 7
Set[s: instr, m:[state: ByteTopSig[5]], d:[state: 8], out: m]; -- 8..15
Set[s: instr, m:[state: ByteTopSig[4]], d:[state:16], out: m]; -- 16..31
Set[s: instr, m:[state: ByteTopSig[8]], d:[state:32], out: m]; -- 32
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 33], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg:  [ s, offset, minus1 ], -- Remainder source
bReg:  [ s, offset, zero ],  -- Divisor
cReg:  [ s, offset, minus1 ], -- Remainder destination
aluOp: DivAdjQ ]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 34], out:[
nextMacro: hold,
pcNext: fromPCBus,
microCycleNext: next,
aReg:  [ s, offset, minus1 ], -- Remainder source
bReg:  [ s, offset, zero ],  -- Divisor
cReg:  [ s, offset, minus1 ], -- Remainder destination
aluOp: DivAdjR ]];
Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 36], out:[
nextMacro: get,
cReg:  [ s, offset, minus2 ], -- Quotient destination
aluOp: RdMQ ]];
};
END.