<> <> <> <> <> <> <<>> DIRECTORY DragOpsCross, IFUPLAInstrDecode, PLAOps; IFUPLAInstrDecodeImpl2: CEDAR PROGRAM IMPORTS IFUPLAInstrDecode, PLAOps EXPORTS IFUPLAInstrDecode = BEGIN OPEN IFUPLAInstrDecode, PLAOps; GenInstrDecodePLA2: PUBLIC GenInstrDecodePLAProc = { instr: BoolExpr; userMode0: BoolExpr _ BE[m:[userMode0: TRUE], d:[userMode0: TRUE]]; current _ old; <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<>> Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRB], out:[ aReg: abStackTop, x2ALitSource: alpha, cReg: cStackTop, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRSB], out:[ aReg: abStackTop, x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLRI0], out:[ aReg: [ l, op47 ], x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; <<>> Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLGF], out:[ -- Save me for lisp aReg: [ aBase , offset, zero ], x2ALitSource: alphaBeta, cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRRI], out:[ aReg: [ l, beta47], x2ALitSource: alpha, cReg: [ l, beta03 ], aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dRAI], out:[ aReg: [ aBase, beta47], x2ALitSource: alpha, cReg: [ l, beta03 ], aluOp: VAdd, dPCmnd: Fetch, dPCmndIsRd0: TRUE ]]; instr _ And[current, BE[m:[op: InstrTopSig[8]], d:[op: dCST]]]; Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 0], out:[ nextMacro: hold, pcNext: fromPCBus, microCycleNext: next, x2ALitSource: zero, aReg: [ cBase, offset, zero ], bReg: [ s, offset, zero ], aluOp: VAdd, dPCmnd: IOStore ]]; Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 1], out:[ nextMacro: hold, pcNext: fromPCBus, microCycleNext: next, x2ALitSource: zero, aReg: [ cBase, offset, one ], bReg: [ s, offset, minus1 ], aluOp: VAdd, dPCmnd: IOStore ]]; Set[s: instr, m:[state: ByteTopSig[8]], d:[state: 2], out:[ x2ALitSource: alpha, aReg: [ s, offset, minus2 ], cReg: [ s, offset, one ], pushSc: TRUE, aluOp: VAdd, dPCmnd: FetchSpecial, dPCmndIsRd0: TRUE ]]; <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <> <<([S-2]+alpha)^ _ [S-1], release hold, S _ S+1>> <<>> <> <<>> <> <> <> <> <> <> <> Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWB]]], out: [ aReg: abStackTop, bReg: [ s, offset, minus1 ], x2ALitSource: alpha, popSa: TRUE, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWSB]]], out: [ aReg: [ s, offset, minus1 ], bReg: abStackTop, x2ALitSource: alpha, popSa: TRUE, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dPSB]]], out: [ aReg: [ s, offset, minus1 ], bReg: abStackTop, x2ALitSource: alpha, popSa: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s: And[current, BE[m:[op: InstrTopSig[4]], d:[op: dSRI0]]], out: [ aReg: [ l, op47 ], bReg: abStackTop, x2ALitSource: alpha, popSb: TRUE, aluOp: VAdd, dPCmnd: Store ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWRI]]], out: [ aReg: [ l, beta47], bReg: [ l, beta03 ], x2ALitSource: alpha, aluOp: VAdd, dPCmnd: Store ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dWAI]]], out: [ aReg: [ aBase, beta47], bReg: [ l, beta03 ], x2ALitSource: alpha, aluOp: VAdd, dPCmnd: Store ]]; <> <> <> <> <<>> <> <> <> <<>> <> <> <> Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIODA]],BE[m:[beta:1],d:[beta:0]]], out: [ aReg: abStackTop, <> cReg: cStackTop, <> x2ALitSource: alpha, aluOp: VAdd, dPCmndSel: beta, dPCmndIsRd0: TRUE]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIODA]],BE[m:[beta:1], d:[beta:1]]],out:[ aReg: abStackTop, popSa: TRUE, bReg: [s, offset, minus1], popSb: TRUE, x2ALitSource: alpha, aluOp: VAdd, dPCmndSel: beta ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOD]], BE[m:[beta:1], d:[beta:0]]], out: [ aReg: constantZero, cReg: [s, offset, one], pushSc: TRUE, x2ALitSource: alpha, aluOp: Or, dPCmndSel: beta, dPCmndIsRd0: TRUE]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dIOD]], BE[m:[beta:1], d:[beta:1]]], out: [ aReg: constantZero, bReg: abStackTop, popSb: TRUE, x2ALitSource: alpha, aluOp: Or, dPCmndSel: beta ]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dION]], BE[m:[beta:1], d:[beta:0]]], out: [ aReg: constantZero, cReg: [s, offset, one], <> x2ALitSource: alpha, aluOp: Or, dPCmndSel: beta, dPCmndIsRd0: TRUE]]; Set[s: And[current, BE[m:[op: InstrTopSig[8]], d:[op: dION]], BE[m:[beta:1], d:[beta:1]]], out: [ aReg: constantZero, bReg: abStackTop, x2ALitSource: alpha, aluOp: Or, dPCmndSel: beta ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dFSDB], out:[ aluOp: VAdd, aReg: [s, offset, zero], x2ALitSource: alphaBeta, cReg: euField, cIsField0: TRUE, popSa: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIB], out:[ x2ALitSource: alpha, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIDB], out:[ x2ALitSource: alphaBeta, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dLIQB], out:[ x2ALitSource: alpBetGamDel, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[5]], d:[op: dLC0], out:[ bReg: [ cBase, op47 ], cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dLR0], out:[ bReg: [ l, op47 ], cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[4]], d:[op: dSR0], out:[ bReg: [ s, offset, zero ], cReg: [ l, op47 ], popSb: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dDUP], out:[ bReg: abStackTop, cReg: [ s, offset, one ], pushSc: TRUE ]]; Set[s:current, m:[op: InstrTopSig[8]], d:[op: dEXDIS], out:[ bReg: abStackTop, cReg: [ s, offset, minus1 ], popSa: TRUE ]]; }; END.