
<<IFUPLAInstrDecode5.mesa>>
<<Copyright c 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT>>
<<Last edited by Curry, September 24, 1985 5:49:06 pm PDT>>
    <<Herrmann, August 14, 1985 4:07:33 pm PDT>>
    <<McCreight, October 18, 1985 12:27:12 pm PDT>>
<<>>
DIRECTORY
Commander,
DragOpsCross,
IFUPLA,
IO,
PLAOps,
Rope;

IFUPLAInstrDecode5: CEDAR PROGRAM
IMPORTS Commander, IFUPLA, IO, PLAOps, Rope EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PLAOps;


GenInstrDecodePLA5:  PUBLIC GenInstrDecodePLAProc = {

instr:                BoolExpr;
aOpt:                BoolExpr    _ BE[m:[alpha: 200B],    d:[alpha: 200B]];
bOpt:                BoolExpr    _ BE[m:[alpha: 040B],    d:[alpha: 040B]];
cOpt:                BoolExpr    _ BE[m:[alpha: 100B],    d:[alpha: 100B]];
aux:                BoolExpr    _ BE[m:[alpha: 020B],    d:[alpha: 020B]];
src0:                BoolExpr    _ BE[m:[alpha: 300B],    d:[alpha: 0B]];
src1:                BoolExpr    _ BE[m:[alpha: 300B],    d:[alpha: 100B]];
srTop:                BoolExpr    _ BE[m:[alpha: 200B],    d:[alpha: 200B]];
srPop:                BoolExpr    _ BE[m:[alpha: 300B],    d:[alpha: 300B]];

current _ old;
<<>>
<<dRR>>
instr    _ And[current, BE[m:[op: InstrTopSig[4]], d:[op: dROR]]];

<<AReg>>
Set[s: And[    Not[aOpt],            aux,    instr],                out:[aReg:[ aBase,    beta47]]];
Set[s: And[    Not[aOpt],        Not[aux],    instr],                out:[aReg:[ l,            beta47]]];
Set[s: And[aOpt,    instr],    m:[beta: 010B],    d:[beta: 000B],    out:[aReg:[ cBase,    beta47]]];
Set[s: And[aOpt,    instr],    m:[beta: 004B],    d:[beta: 000B],    out:[aReg:[ cBase,    beta47]]];
Set[s: And[aOpt,    instr],    m:[beta: 015B],    d:[beta: 014B],    out:[aReg:[ s, offset, zero]]];
Set[s: And[aOpt,    instr],    m:[beta: 015B],    d:[beta: 015B],    out:[aReg:[ s, offset, minus1]]];
<<BReg>>
Set[s: And[ Not[bOpt],            aux,    instr],                    out:[bReg:[ aBase,    alpha47]]];
Set[s: And[ Not[bOpt],        Not[aux],    instr],                    out:[bReg:[ l,            alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 010B],    d:[alpha: 000B],    out:[bReg:[ cBase,    alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 004B],    d:[alpha: 000B],    out:[bReg:[ cBase,    alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 015B],    d:[alpha: 014B],    out:[bReg:[ s, offset, zero]]];
Set[s: And[bOpt,    instr],    m:[alpha: 015B],    d:[alpha: 015B],    out:[bReg:[ s, offset, minus1]]];
<<CReg>>
Set[s: And[ Not[cOpt],        aux,    instr],                        out:[cReg:[ aBase,    beta03]]];
Set[s: And[ Not[cOpt],    Not[aux],    instr],                        out:[cReg:[ l,            beta03]]];
Set[s: And[cOpt,    instr],    m:[beta: 200B],    d:[beta: 000B],    out:[cReg:[ cBase,    beta03]]];
Set[s: And[cOpt,    instr],    m:[beta: 100B],    d:[beta: 000B],    out:[cReg:[ cBase,    beta03]]];
Set[s: And[cOpt,    instr],    m:[beta: 360B],    d:[beta: 300B],    out:[cReg:[ s, offset, zero]]];
Set[s: And[cOpt,    instr],    m:[beta: 360B],    d:[beta: 320B],    out:[cReg:[ s, offset, minus1]]];
Set[s: And[cOpt,    instr],    m:[beta: 340B],    d:[beta: 340B],    out:[cReg:[ s, offset, one]]];
<<Stack>>
Set[s: And[aOpt,    instr], m:[beta:    016B],    d:[beta:    016B],    out:[popSa:            TRUE]];
Set[s: And[bOpt,    instr], m:[alpha:    016B],    d:[alpha:    016B],    out:[popSb:            TRUE]];
Set[s: And[cOpt,    instr], m:[beta:    340B],    d:[beta:    340B],    out:[pushSc:            TRUE]];
<<Body of microinstruction with exceptions>>
Set[s: instr,                                                        out:[aluOpIsOp47:    TRUE]];
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:dRADD],    out:[condSel:            OvFl]];
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:dRLADD],    out:[condSel:            IL]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dRBC],    out:[condSel:            BC]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dRRX],    out:[
dpCmnd:            Fetch,
dpCmndIsRd:        TRUE]];

<<Quick Arithmetic Logicals>>
instr    _ And[current, BE[m:[op: InstrTopSig[5]], d:[op: dQOR]]];
Set[s: instr,    out: [
aluOpIsOp47:    TRUE,
cReg: [s, offset, zero]]];
<<AReg>>
Set[s: And[ src0,            instr],                    out:[aReg:[ cBase, offset, zero]]];
Set[s: And[ src1,            instr],                    out:[aReg:[ cBase, offset, one]]];
Set[s: And[ srTop,        instr],                    out:[aReg:[ s, offset, zero]]];
<<BReg>>
Set[s: And[ Not[bOpt],            aux,    instr],                    out:[bReg:[ aBase,    alpha47]]];
Set[s: And[ Not[bOpt],        Not[aux],    instr],                    out:[bReg:[ l,            alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 010B],    d:[alpha: 000B],    out:[bReg:[ cBase,    alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 004B],    d:[alpha: 000B],    out:[bReg:[ cBase,    alpha47]]];
Set[s: And[bOpt,    instr],    m:[alpha: 015B],    d:[alpha: 014B],    out:[bReg:[ s, offset, zero]]];
Set[s: And[bOpt,    instr],    m:[alpha: 015B],    d:[alpha: 015B],    out:[bReg:[ s, offset, minus1]]];
<<Stack -- these adjustments don't make any sense in QR instructions, but they're included for completeness. Ugh!!>>
Set[s: And[srPop,    instr],                                        out:[popSa:            TRUE]];
Set[s: And[bOpt,    instr], m:[beta:    016B],    d:[beta:    016B],    out:[popSb:            TRUE]];
<<Body of microinstruction with exceptions>>
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:  dQADD],    out:[condSel:            OvFl]];
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:dQLADD],    out:[condSel:            IL]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dQBC],    out:[condSel:            BC]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dQRX],    out:[
dpCmnd:            Fetch,
dpCmndIsRd:        TRUE]];

<<Stack Arithmetic Logicals>>
instr    _ And[current, BE[m:[op: InstrTopSig[5]], d:[op: dOR]]];
Set[s: instr,    out: [
aluOpIsOp47:    TRUE,
aReg: [s, offset, minus1],
bReg: [s, offset, zero],
cReg: [s, offset, minus1],
popSa: TRUE ]];
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:  dADD],    out:[condSel:            OvFl]];
Set[s: instr,    m:[op:    InstrTopSig[7]],        d:[op:dLADD],    out:[condSel:            IL]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dBC],    out:[condSel:            BC]];
Set[s: instr,    m:[op:    InstrTopSig[8]],        d:[op:    dRX],    out:[
dpCmnd:            Fetch,
dpCmndIsRd:        TRUE]] };

GenInstrDecodePLAXops: GenInstrDecodePLAProc = {    -- best to be explicit about this
single, multiple: BoolExpr;
current _ old;

single _                 BE[m:[op: InstrTopSig[4]], d:[op: dTrap]];            -- 16 one byte traps
single _ Or[single, BE[m:[op: InstrTopSig[5]], d:[op: VAL[30B]]]];        -- 8 one byte traps

single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x112B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x117B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x120B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x121B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x122B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x123B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x125B]]];            -- 1 one byte trap
single _ Or[single, BE[m:[op: InstrTopSig[5]], d:[op: VAL[130B]]]];    -- 8 one byte traps

multiple _                 BE[m:[op: InstrTopSig[4]], d:[op: VAL[040B]]];        -- 16 five byte traps
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x060B]]];    -- 1 five byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x063B]]];    -- 1 five byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x064B]]];    -- 1 five byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x065B]]];    -- 1 five byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[5]], d:[op: VAL[070B]]]];    -- 8 five byte traps

multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x215B]]];    -- 1 two byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x223B]]];    -- 1 two byte trap

multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x323B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x337B]]];    -- 1 three byte trap

multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x364B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x365B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x366B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x367B]]];    -- 1 three byte trap

multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x374B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x375B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x376B]]];    -- 1 three byte trap
multiple _ Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x377B]]];    -- 1 three byte trap

Set[s: And[ current,    single],        out: SingleByteXop];
Set[s: And[ current,    multiple],    out: MultiByteXop] };

GenInstrDecode: Commander.CommandProc = {
BE: IDBE = {
mRef:        REF InstrDecodeIn    _ NARROW[instrDecodePLA.mask];
dRef:        REF InstrDecodeIn    _ NARROW[instrDecodePLA.data];
mRef^ _ m; dRef^ _ d; RETURN[GetBEForDataMask[instrDecodePLA]]};
Set: IDSet = {
res:    REF InstrDecodeOut    _ NARROW[instrDecodePLA.out];
<<This should work since:>>
<<kIsRtOp is already set by LIP and KFC,>>
<<xaSource is always set autonomously,>>
<<FOPK is NOT one of the defined RR,Q etc ops which can be substituted with aluOpIsOp47.>>
out.kIsRtOp _ out.kIsRtOp OR (out.xaSource#none) AND (out.aluOp#FOPK);
IF out.aReg.lt=s    OR out.aReg.lt=l    THEN out.aReg.mod _ half;
IF out.bReg.lt=s    OR out.bReg.lt=l    THEN out.bReg.mod _ half;
IF out.cReg.lt=s    OR out.cReg.lt=l    THEN out.cReg.mod _ half;
IF s=NIL
THEN    s    _            BE[m,d]
ELSE    s    _ And[s,    BE[m,d] ];
res^ _ out; SetOutForBE[instrDecodePLA, s]};
SimpleReduce: PROC[pla: PLA] = {
[ ] _ ConvertTermListToCompleteSum[pla.termList, FALSE, FALSE, cmd.out];
[ ] _ FindAMinimalCover[pla.termList, 120, cmd.out]};
filename:    IO.ROPE _ DefaultCMDLine[cmd.commandLine, defaultFile.Cat[".ttt"]];
root:        IO.ROPE    _ filename.Substr[0, filename.Index[0,"."]];
refs:        ARRAY [0..InstrDecodeOutCount) OF IO.ROPE _ [
"IFUPLA.InstrDecodeOut0",
"IFUPLA.InstrDecodeOut1",
"IFUPLA.InstrDecodeOut2",
"IFUPLA.InstrDecodeOut3",
"IFUPLA.InstrDecodeOut4",
"IFUPLA.InstrDecodeOut5",
"IFUPLA.InstrDecodeOut6" ];
curState:            BoolExpr;
instrDecodePLA    _ NewPLA["IFUPLA.InstrDecodeIn", "IFUPLA.InstrDecodeOut"];

curState _ GenInstrDecodePLA1        [BE, Set, curState];
curState _ GenInstrDecodePLA2        [BE, Set, curState];
curState _ GenInstrDecodePLA3        [BE, Set, curState];
curState _ GenInstrDecodePLA4        [BE, Set, curState];
curState _ GenInstrDecodePLA5        [BE, Set, curState];
curState _ GenInstrDecodePLAXops    [BE, Set, curState];
SimpleReduce[instrDecodePLA];
WritePLAFile[filename, cmd.out, instrDecodePLA];
FOR i: INT IN [0..InstrDecodeOutCount) DO
subPla: PLA _ CopyPLASubFields[instrDecodePLA, refs[i] ];
SimpleReduce[subPla];
WritePLAFile[
fileName:    IO.PutFR["%g%g.ttt", IO.rope[root], IO.int[i]],
log:        cmd.out,
pla:        subPla ] ENDLOOP };


defaultFile:        IO.ROPE = "IFUPLAInstrDecode";
doc:                IO.ROPE = "Expects the name of a ttt file";
Commander.Register[key:"GenInstrDecode",        proc: GenInstrDecode,    doc: doc];

END.