GenInstrDecodePLA5:
PUBLIC GenInstrDecodePLAProc = {
instr: BoolExpr;
aOpt: BoolExpr ← BE[m:[alpha: 200B], d:[alpha: 200B]];
bOpt: BoolExpr ← BE[m:[alpha: 040B], d:[alpha: 040B]];
cOpt: BoolExpr ← BE[m:[alpha: 100B], d:[alpha: 100B]];
aux: BoolExpr ← BE[m:[alpha: 020B], d:[alpha: 020B]];
src0: BoolExpr ← BE[m:[alpha: 300B], d:[alpha: 0B]];
src1: BoolExpr ← BE[m:[alpha: 300B], d:[alpha: 100B]];
srTop: BoolExpr ← BE[m:[alpha: 200B], d:[alpha: 200B]];
srPop: BoolExpr ← BE[m:[alpha: 300B], d:[alpha: 300B]];
current ← old;
dRR
instr ← And[current, BE[m:[op: InstrTopSig[4]], d:[op: dROR]]];
AReg
Set[s: And[ Not[aOpt], aux, instr], out:[aReg:[ aBase, beta47]]];
Set[s: And[ Not[aOpt], Not[aux], instr], out:[aReg:[ l, beta47]]];
Set[s: And[aOpt, instr], m:[beta: 010B], d:[beta: 000B], out:[aReg:[ cBase, beta47]]];
Set[s: And[aOpt, instr], m:[beta: 004B], d:[beta: 000B], out:[aReg:[ cBase, beta47]]];
Set[s: And[aOpt, instr], m:[beta: 015B], d:[beta: 014B], out:[aReg:[ s, offset, zero]]];
Set[s: And[aOpt, instr], m:[beta: 015B], d:[beta: 015B], out:[aReg:[ s, offset, minus1]]];
BReg
Set[s: And[ Not[bOpt], aux, instr], out:[bReg:[ aBase, alpha47]]];
Set[s: And[ Not[bOpt], Not[aux], instr], out:[bReg:[ l, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 010B], d:[alpha: 000B], out:[bReg:[ cBase, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 004B], d:[alpha: 000B], out:[bReg:[ cBase, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 015B], d:[alpha: 014B], out:[bReg:[ s, offset, zero]]];
Set[s: And[bOpt, instr], m:[alpha: 015B], d:[alpha: 015B], out:[bReg:[ s, offset, minus1]]];
CReg
Set[s: And[ Not[cOpt], aux, instr], out:[cReg:[ aBase, beta03]]];
Set[s: And[ Not[cOpt], Not[aux], instr], out:[cReg:[ l, beta03]]];
Set[s: And[cOpt, instr], m:[beta: 200B], d:[beta: 000B], out:[cReg:[ cBase, beta03]]];
Set[s: And[cOpt, instr], m:[beta: 100B], d:[beta: 000B], out:[cReg:[ cBase, beta03]]];
Set[s: And[cOpt, instr], m:[beta: 360B], d:[beta: 300B], out:[cReg:[ s, offset, zero]]];
Set[s: And[cOpt, instr], m:[beta: 360B], d:[beta: 320B], out:[cReg:[ s, offset, minus1]]];
Set[s: And[cOpt, instr], m:[beta: 340B], d:[beta: 340B], out:[cReg:[ s, offset, one]]];
Stack
Set[s: And[aOpt, instr], m:[beta: 016B], d:[beta: 016B], out:[popSa: TRUE]];
Set[s: And[bOpt, instr], m:[alpha: 016B], d:[alpha: 016B], out:[popSb: TRUE]];
Set[s: And[cOpt, instr], m:[beta: 340B], d:[beta: 340B], out:[pushSc: TRUE]];
Body of microinstruction with exceptions
Set[s: instr, out:[aluOpIsOp47: TRUE]];
Set[s: instr, m:[op: InstrTopSig[7]], d:[op:dRADD], out:[condSel: OvFl]];
Set[s: instr, m:[op: InstrTopSig[7]], d:[op:dRLADD], out:[condSel: IL]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dRBC], out:[condSel: BC]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dRRX], out:[
dpCmnd: Fetch,
dpCmndIsRd: TRUE]];
Quick Arithmetic Logicals
instr ← And[current, BE[m:[op: InstrTopSig[5]], d:[op: dQOR]]];
Set[s: instr, out: [
aluOpIsOp47: TRUE,
cReg: [s, offset, zero]]];
AReg
Set[s: And[ src0, instr], out:[aReg:[ cBase, offset, zero]]];
Set[s: And[ src1, instr], out:[aReg:[ cBase, offset, one]]];
Set[s: And[ srTop, instr], out:[aReg:[ s, offset, zero]]];
BReg
Set[s: And[ Not[bOpt], aux, instr], out:[bReg:[ aBase, alpha47]]];
Set[s: And[ Not[bOpt], Not[aux], instr], out:[bReg:[ l, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 010B], d:[alpha: 000B], out:[bReg:[ cBase, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 004B], d:[alpha: 000B], out:[bReg:[ cBase, alpha47]]];
Set[s: And[bOpt, instr], m:[alpha: 015B], d:[alpha: 014B], out:[bReg:[ s, offset, zero]]];
Set[s: And[bOpt, instr], m:[alpha: 015B], d:[alpha: 015B], out:[bReg:[ s, offset, minus1]]];
Stack -- these adjustments don't make any sense in QR instructions, but they're included for completeness. Ugh!!
Set[s: And[srPop, instr], out:[popSa: TRUE]];
Set[s: And[bOpt, instr], m:[beta: 016B], d:[beta: 016B], out:[popSb: TRUE]];
Body of microinstruction with exceptions
Set[s: instr, m:[op: InstrTopSig[7]], d:[op: dQADD], out:[condSel: OvFl]];
Set[s: instr, m:[op: InstrTopSig[7]], d:[op:dQLADD], out:[condSel: IL]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dQBC], out:[condSel: BC]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dQRX], out:[
dpCmnd: Fetch,
dpCmndIsRd: TRUE]];
Stack Arithmetic Logicals
instr ← And[current, BE[m:[op: InstrTopSig[5]], d:[op: dOR]]];
Set[s: instr, out: [
aluOpIsOp47: TRUE,
aReg: [s, offset, minus1],
bReg: [s, offset, zero],
cReg: [s, offset, minus1],
popSa: TRUE ]];
Set[s: instr, m:[op: InstrTopSig[7]], d:[op: dADD], out:[condSel: OvFl]];
Set[s: instr, m:[op: InstrTopSig[7]], d:[op:dLADD], out:[condSel: IL]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dBC], out:[condSel: BC]];
Set[s: instr, m:[op: InstrTopSig[8]], d:[op: dRX], out:[
dpCmnd: Fetch,
dpCmndIsRd: TRUE]] };
GenInstrDecodePLAXops: GenInstrDecodePLAProc = {
-- best to be explicit about this
single, multiple: BoolExpr;
current ← old;
single ← BE[m:[op: InstrTopSig[4]], d:[op: dTrap]]; -- 16 one byte traps
single ← Or[single, BE[m:[op: InstrTopSig[5]], d:[op: VAL[30B]]]]; -- 8 one byte traps
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x112B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x117B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x120B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x121B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x122B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x123B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[8]], d:[op: x125B]]]; -- 1 one byte trap
single ← Or[single, BE[m:[op: InstrTopSig[5]], d:[op: VAL[130B]]]]; -- 8 one byte traps
multiple ← BE[m:[op: InstrTopSig[4]], d:[op: VAL[040B]]]; -- 16 five byte traps
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x060B]]]; -- 1 five byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x063B]]]; -- 1 five byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x064B]]]; -- 1 five byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x065B]]]; -- 1 five byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[5]], d:[op: VAL[070B]]]]; -- 8 five byte traps
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x215B]]]; -- 1 two byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x223B]]]; -- 1 two byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x323B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x337B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x364B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x365B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x366B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x367B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x374B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x375B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x376B]]]; -- 1 three byte trap
multiple ← Or[multiple, BE[m:[op: InstrTopSig[8]], d:[op: x377B]]]; -- 1 three byte trap
Set[s: And[ current, single], out: SingleByteXop];
Set[s: And[ current, multiple], out: MultiByteXop] };
GenInstrDecode: Commander.CommandProc = {
BE:
IDBE = {
mRef: REF InstrDecodeIn ← NARROW[instrDecodePLA.mask];
dRef: REF InstrDecodeIn ← NARROW[instrDecodePLA.data];
mRef^ ← m; dRef^ ← d; RETURN[GetBEForDataMask[instrDecodePLA]]};
Set: IDSet = {
res: REF InstrDecodeOut ← NARROW[instrDecodePLA.out];
This should work since:
kIsRtOp is already set by LIP and KFC,
xaSource is always set autonomously,
FOPK is NOT one of the defined RR,Q etc ops which can be substituted with aluOpIsOp47.
out.kIsRtOp ← out.kIsRtOp OR (out.xaSource#none) AND (out.aluOp#FOPK);
IF out.aReg.lt=s OR out.aReg.lt=l THEN out.aReg.mod ← half;
IF out.bReg.lt=s OR out.bReg.lt=l THEN out.bReg.mod ← half;
IF out.cReg.lt=s OR out.cReg.lt=l THEN out.cReg.mod ← half;
IF s=
NIL
THEN s ← BE[m,d]
ELSE s ← And[s, BE[m,d] ];
res^ ← out; SetOutForBE[instrDecodePLA, s]};
SimpleReduce:
PROC[pla:
PLA] = {
[ ] ← ConvertTermListToCompleteSum[pla.termList, FALSE, FALSE, cmd.out];
[ ] ← FindAMinimalCover[pla.termList, 120, cmd.out]};
filename: IO.ROPE ← DefaultCMDLine[cmd.commandLine, defaultFile.Cat[".ttt"]];
root: IO.ROPE ← filename.Substr[0, filename.Index[0,"."]];
refs:
ARRAY [0..InstrDecodeOutCount)
OF
IO.
ROPE ← [
"IFUPLA.InstrDecodeOut0",
"IFUPLA.InstrDecodeOut1",
"IFUPLA.InstrDecodeOut2",
"IFUPLA.InstrDecodeOut3",
"IFUPLA.InstrDecodeOut4",
"IFUPLA.InstrDecodeOut5",
"IFUPLA.InstrDecodeOut6" ];
curState: BoolExpr;
instrDecodePLA ← NewPLA["IFUPLA.InstrDecodeIn", "IFUPLA.InstrDecodeOut"];
curState ← GenInstrDecodePLA1 [BE, Set, curState];
curState ← GenInstrDecodePLA2 [BE, Set, curState];
curState ← GenInstrDecodePLA3 [BE, Set, curState];
curState ← GenInstrDecodePLA4 [BE, Set, curState];
curState ← GenInstrDecodePLA5 [BE, Set, curState];
curState ← GenInstrDecodePLAXops [BE, Set, curState];
SimpleReduce[instrDecodePLA];
WritePLAFile[filename, cmd.out, instrDecodePLA];
FOR i:
INT
IN [0..InstrDecodeOutCount)
DO
subPla: PLA ← CopyPLASubFields[instrDecodePLA, refs[i] ];
SimpleReduce[subPla];
WritePLAFile[
fileName: IO.PutFR["%g%g.ttt", IO.rope[root], IO.int[i]],
log: cmd.out,
pla: subPla ] ENDLOOP };