
<<IFUPLAImplB4.mesa>>
<<Copyright © 1984 by Xerox Corporation.  All rights reserved.>>
<<Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT>>
<<Last edited by Curry, November 4, 1984 1:31:49 pm PST>>
<<>>
DIRECTORY
Commander,
DragOpsCross,
IFUPLA,
IO,
PLAOps;

IFUPLAImplB4: CEDAR PROGRAM
IMPORTS Commander, IFUPLA, IO, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;


instr:            PO.BoolExpr;

GeneratePhBPLA4:  PUBLIC PROC = {

<<Used in instructions>>
aOpt:                PO.BoolExpr    _ BE[m:[beta: 200B],    d:[beta: 200B]];
bOpt:                PO.BoolExpr    _ BE[m:[beta: 040B],    d:[beta: 040B]];
cOpt:                PO.BoolExpr    _ BE[m:[beta: 100B],    d:[beta: 100B]];
aux:                PO.BoolExpr    _ BE[m:[beta: 020B],    d:[beta: 020B]];
<<>>
<<dRR>>
instr    _ PO.And[current, BE[m:[op: instrBot4NotSig], d:[op: dRADD]]];

<<AReg>>
Set[s: PO.And[    PO.Not[aOpt],            aux,    instr],            out:[aReg:[ aBase,    alpha47]]];
Set[s: PO.And[    PO.Not[aOpt],    PO.Not[aux],    instr],            out:[aReg:[ l,            alpha47]]];
Set[s: PO.And[aOpt,    instr],    m:[alpha: 010B],    d:[alpha: 000B],    out:[aReg:[ cBase,    alpha47]]];
Set[s: PO.And[aOpt,    instr],    m:[alpha: 004B],    d:[alpha: 000B],    out:[aReg:[ cBase,    alpha47]]];
Set[s: PO.And[aOpt,    instr],    m:[alpha: 015B],    d:[alpha: 014B],    out:[aReg:[ s,            zero]]];
Set[s: PO.And[aOpt,    instr],    m:[alpha: 015B],    d:[alpha: 015B],    out:[aReg:[ s,            minus1]]];
<<BReg>>
Set[s: PO.And[ PO.Not[bOpt],            aux,    instr],                out:[bReg:[ aBase,    beta47]]];
Set[s: PO.And[ PO.Not[bOpt],    PO.Not[aux],    instr],                out:[bReg:[ l,            beta47]]];
Set[s: PO.And[bOpt,    instr],    m:[beta: 010B],    d:[beta: 000B],    out:[bReg:[ cBase,    beta47]]];
Set[s: PO.And[bOpt,    instr],    m:[beta: 004B],    d:[beta: 000B],    out:[bReg:[ cBase,    beta47]]];
Set[s: PO.And[bOpt,    instr],    m:[beta: 015B],    d:[beta: 014B],    out:[bReg:[ s,        zero]]];
Set[s: PO.And[bOpt,    instr],    m:[beta: 015B],    d:[beta: 015B],    out:[bReg:[ s,        minus1]]];
<<CReg>>
Set[s: PO.And[ PO.Not[cOpt],        aux,    instr],                    out:[cReg:[ aBase,    alpha03]]];
Set[s: PO.And[ PO.Not[cOpt],    PO.Not[aux],    instr],                out:[cReg:[ l,            alpha03]]];
Set[s: PO.And[cOpt,    instr],    m:[alpha: 200B],    d:[alpha: 000B],    out:[cReg:[ cBase,    alpha03]]];
Set[s: PO.And[cOpt,    instr],    m:[alpha: 100B],    d:[alpha: 000B],    out:[cReg:[ cBase,    alpha03]]];
Set[s: PO.And[cOpt,    instr],    m:[alpha: 360B],    d:[alpha: 300B],    out:[cReg:[ s,            zero]]];
Set[s: PO.And[cOpt,    instr],    m:[alpha: 360B],    d:[alpha: 320B],    out:[cReg:[ s,            minus1]]];
Set[s: PO.And[cOpt,    instr],    m:[alpha: 340B],    d:[alpha: 340B],    out:[cReg:[ s,            one]]];
<<Stack>>
Set[s: PO.And[aOpt,    instr], m:[alpha:    016B],    d:[alpha:    016B],    out:[deltaSa: pop]];
Set[s: PO.And[bOpt,    instr], m:[beta:    016B],    d:[beta:    016B],    out:[deltaSb: pop]];
Set[s: PO.And[cOpt,    instr], m:[alpha:    340B],    d:[alpha:    340B],    out:[deltaSc: push]];
<<Body of microinstruction with exceptions>>
Set[s: instr,                                                    out:[aluOp:    op47]];
Set[s: instr,    m:[op:    instrBot1NotSig],    d:[op:    dRADD],    out:[condSel:    OvFl]]; -- Add or Sub
Set[s: instr,    m:[op:    instrBot1NotSig],    d:[op:dRLADD],    out:[condSel:    IL]];    -- Add or Sub
Set[s: instr,    m:[op:    instrIsSig],        d:[op:    dRBC],    out:[condSel:    BC]];
Set[s: instr,    m:[op:    instrIsSig],        d:[op:    dRBC],    out:[condEffect:    macroTrap]];
Set[s: instr,    m:[op:    instrIsSig],        d:[op:    dRRX],    out:[aluOp:    VAdd]];
Set[s: instr,    m:[op:    instrIsSig],        d:[op:    dRRX],    out:[euPBusCmd: Fetch]];
<<The last four bits of dRRX(1000) Ored with VAdd(1100) converts its RR generated aluOp into VAdd(1100).  This implies that op47 
must be ORed with m.op to generate the real alu op.>>
<<NO NO NO.... aluOp=op47 and aluOp VAdd won't work.  We must use another output bit to say 'AluOp _ Op47 OR micro.AluOp'>>

<<Do Xops>>
instr    _ PO.Or[    -- One Byte instructions
BE[m:[op: instrBot5NotSig], d:[op: LOOPHOLE[000B]]],
BE[m:[op: instrBot6NotSig], d:[op: LOOPHOLE[100B]]] ];
Set[s: PO.And[        instr, PO.Not[UsedOpcodes], current],    out:[    -- One Byte instructions
doMacroJump:        TRUE,
dontGetNextMacro:    TRUE,
xBSource:                xopGenerator,
pipedPLSASpec:        pLenLSnext,
iStackPostEffect:        push ]];
Set[s: PO.And[    PO.Not[instr], PO.Not[UsedOpcodes], current],
m:[state:    byteIsSig],        d:[state:    0],    out:[    -- Multi Byte instructions
doMacroJump:        TRUE,
dontGetNextMacro:    TRUE,
xBSource:                xopGenerator,
pipedPLSASpec:        pLenLSnext,
iStackPostEffect:        push ]];
Set[s: PO.And[    PO.Not[instr], PO.Not[UsedOpcodes], current],
m:[state:    byteIsSig],        d:[state:    1],    out:[    -- Multi Byte instructions
doMacroJump:        TRUE,
dontGetNextMacro:    TRUE,
xBSource:                xopGenerator,
pipedPLSASpec:        pLenLSnext,
iStackPostEffect:        push,
deltaSc:                push ]] };


BE: PUBLIC PROC [m, d: PhBArgs] RETURNS[PO.BoolExpr] = {
mRef:        REF PhBArgs    _ NARROW[PhBPLA.mask];
dRef:        REF PhBArgs    _ NARROW[PhBPLA.data];
mRef^ _ m; dRef^ _ d; RETURN[PO.GetBEForDataMask[PhBPLA]]};

Set: PUBLIC PROC [s: PO.BoolExpr _ NIL,    m, d: PhBArgs _ [ ], out: MicroInst] = {
res:    REF MicroInst    _ NARROW[PhBPLA.out];
IF m.op#dTrap    -- #0 test for significance of opcode
THEN UsedOpcodes _ PO.Or[BE[m:[op:m.op], d:[op:d.op]], UsedOpcodes];
out.aluOpFOP        _ out.aluOp=FOP;
out.notPassRtIfAZero    _ out.aluOp#Or OR (out.euPBusCmd IN [StoreFP..FetchFPMult]);
out.kIsRtOp    _ out.kASource IN [alpha..bReg] AND  (out.aluOp # FOPK);
IF s=NIL
THEN    s    _                BE[m,d]
ELSE    s    _ PO.And[s,    BE[m,d] ];
res^ _ out; PO.SetOutForBE[PhBPLA, s]};


ReadPhBPLA:    PUBLIC PROC[argRec: PhBArgs] RETURNS[resRec: MicroInst] = {
arg:    REF PhBArgs    _ NARROW[PhBPLA.data];
res:    REF MicroInst    _ NARROW[PhBPLA.out];
arg^ _ argRec; PO.GetOutForData[PhBPLA]; resRec _ res^};

UsedOpcodes:    PO.BoolExpr;    -- Built as side effect in PROC Set
PhBPLA:        PUBLIC PO.PLA _ NIL;
current:            PUBLIC PO.BoolExpr;


genDoc:            IO.ROPE = "GenIFUPLAPhB expects the name of the output file";
readDoc:            IO.ROPE = "ReadIFUPLAPhB expects the name of the input file";
defaultFile:        IO.ROPE = "IFUPLAPhB.pla";

GenIFUPLAPhB: Commander.CommandProc = {
filename: IO.ROPE _ PO.DefaultCMDLine[cmd.commandLine, defaultFile];
PhBPLA    _ PO.NewPLA[inName: "IFUPLA.PhBArgs", outName: "IFUPLA.MicroInst"];
GeneratePhBPLA1[];
PO.WritePLAFile[filename, cmd.out, PhBPLA] };

ReadIFUPLAPhB: Commander.CommandProc = {
PhBPLA    _ PO.ReadPLAFile[PO.DefaultCMDLine[cmd.commandLine, defaultFile], cmd.out] };

WriteIFUPLAPhB: Commander.CommandProc = {PO.WritePLAFile
[PO.DefaultCMDLine[cmd.commandLine, defaultFile], cmd.out, PhBPLA] };

Commander.Register[key:"GenIFUPhB",        proc: GenIFUPLAPhB,    doc: genDoc];
Commander.Register[key:"ReadIFUPhB",    proc: ReadIFUPLAPhB,    doc: readDoc];
Commander.Register[key:"WriteIFUPhB",    proc: WriteIFUPLAPhB,    doc: readDoc];

END.