IFUPLAImplB1.mesa
Copyright © 1984 by Xerox Corporation. All rights reserved.
Last edited by TWilliams, August 27, 1984 4:58:00 pm PDT
Last edited by Curry, November 4, 1984 1:31:36 pm PST
DIRECTORY
Basics,
Dragon,
DragOpsCross,
IFUPLA,
PLAOps;
IFUPLAImplB1: CEDAR PROGRAM
IMPORTS IFUPLA, PLAOps EXPORTS IFUPLA =
BEGIN OPEN IFUPLA, PO: PLAOps;
GeneratePhBPLA1: PUBLIC PROC = {
Used in RR and RJB instructions
sdd:  PO.BoolExpr ← BE[m:[beta: 200B], d:[beta: 200B]];
opt:  PO.BoolExpr ← BE[m:[beta: 040B], d:[beta: 040B]];
sd:   PO.BoolExpr ← BE[m:[beta: 100B], d:[beta: 100B]];
aux:  PO.BoolExpr ← BE[m:[beta: 020B], d:[beta: 020B]];
instr, delay, trap, exception:  PO.BoolExpr; -- Temporaries
m: MicroInst;
exception ← BE[m:[stateException: TRUE], d:[stateException: TRUE]];
current ← PO.And[exception, BE[m:[state: prioritySig], d:[state: highPriority]]];
Do High Priority Exceptions
Set[s:current, m:[state: exceptionSig], d:[state: reseting], out: [
doMacroJump: FALSE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,
lSource: [ zero, one ],
sSource: [ zero, zero ] ]];
Set[s:current, m:[state: exceptionSig], d:[state: reset],  out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,
lSource: [ zero, one ],
sSource: [ zero, zero ] ]];
m ← [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,
kASource: bReg,
bReg: ifuLevel3LS,
lSource: [ xBus, zero ],
sSource: [ xBus, zero ],
pushLevel3: TRUE ];
Set[s:current, m:[state: exceptionSig], d:[state: euCC],  out: m];
Set[s:current, m:[state: exceptionSig], d:[state: epFault], out: m];
Set[s:current, m:[state: exceptionSig], d:[state: cJump],  out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pipe3PC,
kASource: bReg,
bReg: ifuLevel3LS,
lSource: [ xBus, zero ],
sSource: [ xBus, zero ] ]];
Delayed Low Priority Exceptions
current ← PO.And[exception, PO.Not[BE[m:[state: prioritySig], d:[state: highPriority]]]];
Set[s:current, m:[stateDelay: TRUE],  d:[stateDelay: TRUE], out: Delayed];
Do Low Priority Exceptions
Set[s:current, m:[stateDelay: TRUE], d:[stateDelay: FALSE], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,
iStackPostEffect: push,
iTrapPostEffect: disable ] ];
Not An Exception
current ← BE[m:[stateException: TRUE], d:[stateException: FALSE]];
Set[s:current, m:[stateDelay: TRUE],  d:[stateDelay: TRUE], out: Delayed];
current ← PO.And[current, BE[m:[stateDelay: TRUE], d:[stateDelay: FALSE]]];
Instruction not ready
Set[s:current, m:[instReady: TRUE], d:[instReady: FALSE], out: Delayed];
current ← PO.And[current, BE[m:[instReady: TRUE],  d:[instReady: TRUE]]];
Check for Delays and IStack Underflow traps in dRET, dRETT, dRETN, dLIFUR
Temporary BE's used by dRET, dRETT, dRETN, dLIFUR
delay ← PO.Or[
BE[m:[pushPending: TRUE], d:[pushPending: TRUE]],
BE[m:[popPending: TRUE],  d:[popPending: TRUE]]];
trap ← PO.And[
PO.Not[delay],
BE[m:[iStkEmpty: TRUE],  d:[iStkEmpty: TRUE]]];
Set[s: PO.And[current, delay],    m:[op: instrIsSig], d:[op: dRET], out: Delayed];
Set[s: PO.And[current, delay],    m:[op: instrIsSig], d:[op: dRETT], out: Delayed];
Set[s: PO.And[current, delay],    m:[op: instrIsSig], d:[op: dRETN], out: Delayed];
m ← [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,  -- IStack Underflow is the default for trapPC
sSource: [ l, alpha ],
iTrapPostEffect: disable ];
Set[s: PO.And[current, trap],      m:[op: instrIsSig], d:[op: dRET], out: m];
m.sSource ← [ s, zero ];
Set[s: PO.And[current, trap],      m:[op: instrIsSig], d:[op: dRETT], out: m];
Set[s: PO.And[current, trap],      m:[op: instrIsSig], d:[op: dRETN], out: m];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]], m:[op: instrIsSig], d:[op: dRET], out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: iStackPC,
kASource: bReg,
bReg: ifuYoungestL,
lSource: [ xBus, zero ],
sSource: [ l, alpha ],
iStackPostEffect: pop ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]], m:[op: instrIsSig], d:[op: dRETT], out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: iStackPC,
kASource: bReg,
bReg: ifuYoungestL,
lSource: [ xBus, zero ],
iStackPostEffect: pop,
iTrapPostEffect: enable ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]], m:[op: instrIsSig], d:[op: dRETN], out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: iStackPC,
kASource: bReg,
bReg: ifuYoungestL,
lSource: [ xBus, zero ],
iStackPostEffect: pop ]];
Set[s: PO.And[current, delay],      m:[op: instrIsSig], d:[op: dLIFUR], out: Delayed];
Set[s: PO.And[current, PO.Not[delay]],    m:[op: instrIsSig], d:[op: dLIFUR], out:[
bReg: [zero, alpha],
kASource: bReg,
cReg: [ s, one ],
deltaSc: push ]];
Check for Delay and IStack Underflow trap in EP
Look for the case of a Call - EP sequence broken by a Reschedule which returns with an empty IStack. EP (L←S+alpha) => that the stack is expected to contain some local values which (if IStack is empty) have been swapped out.
Temporary BE's used by EP:
delay ← PO.And[
BE[m:[popPending: TRUE],   d:[popPending: TRUE]],
BE[m:[iStkEmpty: TRUE],   d:[iStkEmpty: FALSE]]];
trap ← PO.And[
PO.Not[delay],
BE[m:[iStkEmpty: TRUE],   d:[iStkEmpty: TRUE]],
BE[m:[pushPending: TRUE],  d:[pushPending: FALSE]] ];
Set[s: PO.And[current, delay],  m:[op: instrIsSig], d:[op: dEP], out: Delayed];
Set[s: PO.And[current, trap],  m:[op: instrIsSig], d:[op: dEP], out: [
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: trapPCGenerator,
lSource: [ s, alpha ],
pipedPLSASpec: pLenLSnext,
iStackPostEffect: push, -- this push differentiates this trap from the following
iTrapPostEffect: disable ]];
Set[s: PO.And[current, PO.Not[PO.Or[delay, trap]]], m:[op: instrIsSig], d:[op: dEP], out:
[lSource: [ s, alpha]]];
Do the rest of the S and L modifiers here
Set[s:current, m:[op: instrIsSig], d:[op: dDIS], out:[deltaSa: pop]];
Set[s:current, m:[op: instrIsSig], d:[op: dAS],  out:[sSource: [s, alpha]]];
Set[s:current, m:[op: instrIsSig], d:[op: dAL],  out:[lSource: [l, alpha]]];
Set[s:current, m:[op: instrIsSig], d:[op: dASL], out:[sSource: [l, alpha]]];
m ← [
aReg: abStackTop,
kASource: beta,
deltaSa: pop,
aluOp: VSub,
condEffect: macroJump,
condSel: EZ,
doMacroJump: FALSE,
dontGetNextMacro: FALSE,
xBSource: pcPlusLen,
pipedPLSASpec: pAlphasLSnext];
Set[s:current, m:[op: instrIsSig], d:[op: dJEBB], out:m];
m.condSel ← NE;
Set[s:current, m:[op: instrIsSig], d:[op: dJNEBB], out:m];
m ← [
aReg: abStackTop,
kASource: beta,
deltaSa: pop,
aluOp: VSub,
condEffect: macroJump,
condSel: EZ,
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusAlphaS,
pipedPLSASpec: pLenLSnext];
Set[s:current, m:[op: instrIsSig], d:[op: dJNEBBJ], out:m];
m.condSel ← NE;
Set[s:current, m:[op: instrIsSig], d:[op: dJEBBJ], out:m];
dRJ*B and dRJ*BJ - Bit 4 distinguishes between them
instr ← PO.And[current, BE[m:[op: instrBot4NotSig], d:[op: dRJEB]]]; -- RJ*B and RJ*BJ
Main Body
Set[s:current, m:[op: instrBot3NotSig], d:[op: dRJEB], out:[ -- RJ*B
aluOp: VSub,
condSel: op57, -- Low 3 bits distinguish between 2 * 8 Jumps
condEffect: macroJump,
doMacroJump: FALSE,
dontGetNextMacro: FALSE,
xBSource: pcPlusLen,
pipedPLSASpec: pAlphasLSnext] ];
Set[s:current, m:[op: instrBot3NotSig], d:[op: dRJEBJ], out:[ -- RJ*BJ
aluOp: VSub,
condSel: op57,
condEffect: macroJump,
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusAlphaS,
pipedPLSASpec: pLenLSnext] ];
AReg depends only on sd
Set[s: PO.And[  sd, instr], out:[aReg:[ s, minus1 ]]];
Set[s: PO.And[PO.Not[sd], instr], out:[aReg:[ s, zero ]]];
BReg
Set[s: PO.And[ PO.Not[opt],   aux, instr],    out:[bReg:[ aBase, beta47 ]]];
Set[s: PO.And[ PO.Not[opt], PO.Not[aux], instr],    out:[bReg:[ l,   beta47 ]]];
Set[s: PO.And[opt, instr], m:[beta: 010B], d:[beta: 000B], out:[bReg:[ cBase, beta47 ]]];
Set[s: PO.And[opt, instr], m:[beta: 004B], d:[beta: 000B], out:[bReg:[ cBase, beta47 ]]];
Set[s: PO.And[opt, instr], m:[beta: 015B], d:[beta: 014B], out:[bReg:[ s,  zero ]]];
Set[s: PO.And[opt, instr], m:[beta: 015B], d:[beta: 015B], out:[bReg:[ s,  minus1 ]]];
Stack
Set[s: PO.And[sdd, instr],           out:[deltaSa: pop]];
Set[s: PO.And[opt, instr], m:[beta: 016B], d:[beta: 016B], out:[deltaSb: pop]];
Set[s:current, m:[op: instrIsSig], d:[op: dJ1], out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig], d:[op: dJ2], out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig], d:[op: dJ3], out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig], d:[op: dJ5], out:DefaultMicro]; -- Just too mark as ~Xops
Set[s:current, m:[op: instrIsSig], d:[op: dJB], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusAlphaS ]];
Set[s:current, m:[op: instrIsSig], d:[op: dJDB], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusBetaAlphaS ]];
Set[s:current, m:[op: instrIsSig], d:[op: dDJ], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: deltaGammaBetaAlpha ]];
instr ← PO.And[current, BE[m:[op: instrIsSig], d:[op: dSJ]]];
Set[s:instr, m:[state: byteIsSig], d:[state: 0], out:[ -- ifuXBus ← [S]
dontGetNextMacro: TRUE,
xBSource: pc,
bReg: abStackTop,
cReg: ifuXBus ]];
Set[s:instr, m:[state: byteIsSig], d:[state: 1], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 2], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 3], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 4], out:[ -- S ← S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusXA,
deltaSa: pop ]];
Set[s:current, m:[op: instrIsSig], d:[op: dLFC], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: pcPlusBetaAlphaS,
pipedPLSASpec: pLenLSnext,
iStackPostEffect: push ]];
Set[s:current, m:[op: instrIsSig], d:[op: dDFC], out:[
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: deltaGammaBetaAlpha,
pipedPLSASpec: pLenLSnext,
iStackPostEffect: push ]];
instr ← PO.And[current, BE[m:[op: instrIsSig], d:[op: dSFC]]];
Set[s:instr, m:[state: byteIsSig], d:[state: 0], out:[ -- ifuXBus ← [S]
dontGetNextMacro: TRUE,
xBSource: pc,
bReg: abStackTop,
cReg: ifuXBus ]];
Set[s:instr, m:[state: byteIsSig], d:[state: 1], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 2], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 3], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 4], out:[ -- S ← S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: xA,
deltaSa: pop,
pipedPLSASpec: pLenLSnext,
iStackPostEffect: push ]];
instr ← PO.And[current, BE[m:[op: instrIsSig], d:[op: dSFCI]]];
Set[s:instr, m:[state: byteIsSig], d:[state: 0], out:[ -- ifuXBus ← [S]^
dontGetNextMacro: TRUE,
xBSource: pc,
bReg: abStackTop,
cReg: ifuXBus,
euPBusCmd: Fetch ]];
Set[s:instr, m:[state: byteIsSig], d:[state: 1], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 2], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 3], out:NoOpMicro]; -- to allow Xa to latch Result3
Set[s:instr, m:[state: byteIsSig], d:[state: 4], out:[ -- S ← S-1
doMacroJump: TRUE,
dontGetNextMacro: TRUE,
xBSource: xA,
deltaS: 0, -- shouldn't SFCI pop S?
pipedPLSASpec: pLenLSnext,
iStackPostEffect: push ]];
GeneratePhBPLA2[]; -- Arbitrary break
}; -- of GeneratePhBPLA1
END.