Multiprocessor shared-bus computer architectures have several key hardware requirements. Most important is bus bandwidth as this limits the number of processors and other facilities which can share the bus without overloading. A flexible architecture is important to allow a system to be used for different applications.

This paper describes a high bandwidth bus (HBB) built with multichip modules (MCM). The high bandwidth is accomplished in two ways. First, the shared-bus is shortented by segmentation into many shorter buses with fewer components attached. This bus shortening reduces bus propagation time and hense facilitates shorter clock cycles. The other key element is increasing the bus width. Multichip packaging is used to accomodate the increased IC pincount (resulting from the wide bus) and to reduce the system size. The high package pincount is accomodated by a dense high-speed board connector.

The high bandwidth bus to be described here is a system shell and contains no processing or memory functionality. The architecture allows a separation between the bus electronics and the system core.

The high bandwidth bus has been built to test the use of MCM. The bus has been segmentated on two levels as shown in Fig 1. The lowest level is inside the MCM. Here several component IC's are connected on a MCM and share a common bus. The package is small enough (2.4" x 3.2") so that the bus requires no termination operating at frequencies up to ss MHz. In addition, signals experience substantially less loading on the MCM where line capacitances are approximately 1pF/cm. For the packages discussed here the maximum off-chip loading capacitance is 15pF.

The next level bus is the board bus which connects 5 MCMs. The board bus is a terminated 50W stripline approximately 40cm in length. The bus consists of 8 mil traces separated by x mils. A ground trace is placed between each signal line to minimize crosstalk.

The bandwidth can be increased by using wider buses at the cost of additional pins on both the MCMs and the ICs. The high pin-count ICs are connected to the MCMs using conventional wirebonding on a 7 mil pitch. Eight interface ICs with 160 pins have been bonded to the MCM.

The ICs are place at the edge of the MCM and are designed to comunicate with the 2V level board bus on one side and the 5V level on the MCM bus. The interface used here has been fabricated in 2 mm CMOS. Open collector n-channel devices are used to sink the 2V board bus and a xxxx is used to sense the level. CMOS drivers are used for input/output on the MCM. Since in this implementation the interface chips are separate from the functional logic bipolar technology could be used. Considerable additional space exists in the middle each MCM for additional ICs which would communicate through the interface chips to the board bus.

The MCM is connected to the board using a high-speed connector with pins on 25mil centers. The connector connects pads on all four sides of the package. The bus connections are made on two opposite sides with the bus passing underneath the package. A block of vias is needed to connect the surface pads to the bus traces underneath and the width of the block will determine the mininmum package size for a given board technology.

The MCM (Fig. x) consists of 4 levels of metal interconnect fabricated on the surface on a silicon wafer using IC processing technology. The interconnect is 5mm thick aluminum and has a minimum width of 1 mil with a 4 mil separation from adjacent features. The metal levels are separated by an insulating polyimide film and connected through 15mm vias. The ICs and decoupling capacitors are attached with epoxy.

The MCM is connected to the board through a mechanical connector (Fig. x)a. The connector, designed for use in high speed systems, contributes less than xpF capacitance to the stub and has less than ynF of inductance. The stubs on the MCM are kept short (1cm) to keep the total loading on the bus less than zpF. The groundplane is removed in the vicinity of the point of attachment of the MCM the board to accomadate the local stub capacitance. The connector design allows the MPCs to be easily replaced.

The substrate is mounted with the ICs facing the board so that heat can be transferred through a heat sink to air forced across the board (Fig. A). The thermal resistance from the IC surface to the heat sink is approximately xC/W.

Electronics