Last Edited by: Louis Monier June 22, 1986 10:32:34 pm PDT
An account of bugs and difficulties encountered towards the end of EU2's design. Hope they will help future designs.
Representation: schematics and code
It is hard (and boring) to draw large things; it is hard to visualize Core structures produced from code. The art is to balance between the two means of description.
Main modules (CoreOps and such) need better bullet-proofing, so that they catch errors early. Typical: a NIL wire will survive until you look for his name. Main problem was to keep consistent these long lists of wires. I should have drawn more and coded less!
Layout: ChipNDale, PWCore and routers
Too bad we didn't have a general router to which I could have handed my four blocks and let it operate and place pads. A lot of time was spent listing wires out of one channel and into the next one.
DRC: bugs caught by SOS and the Gismos
The basic cells were checked interactively and most common errors (metal sep., ndiff/pdiff sep.) were eliminated at this stage. Layout constraints at the edge of cells insured that no error was created when abutting cells, and DRC of the whole datapath showed no error.
The main problem was to make sure that the DRC and I were aggreeing on the design rules.
Things I fixed late in the game, in almost every cell, but in a few main classes centered around the fuzzy design rules:
Via sizes: after a long debate, the via size was restricted to 5x5, with a notable exception for pads openings. The optimum size was found to be 4x4 as far as current carrying capability goes, so all large vias were resized.
Contact cut separation: no longer 2 but 3.
Separation between gate and well diffusion in the case of a split contact. Very ambiguous rule.
One case of via on poly: not really an error, but discouraged, so I choose to be conservative.
Bugs caught by Lichen
Ram multiplexer: the schematics was wrong, layout OK. A wire had been shortened and was making contact where it should not have. Net list was really wrong.
Ram multiplexer: A substrate contact was sitting on a Gnd metal2 bus, without via. Lichen detected the extra internal wire.
Alu function block: the Nand gate inside a XNor gate was laid out as a Nor. Leftover from the time when it was a Xor gate.
Alu function block: complementary inputs were permuted.
IOTst Pad: a compex gate (8 transistors) had been redesign by another designer.
Output pad: schematics was wrong; reference to Vdd and Gnd instead of PadVdd adn PadGnd. Layout was correct.
Bugs caught by Rosemary
Enable write for KBus driver receive both enPhA and enPhB: equations were permuted.
Output of shift register was connected to input pad, and conversely, though designer input was thouroughy checked and found correct. Undeterministic bug was deep in Sisyph, and caused random binding of unnamed wires.
ALU function block: the sum was inverted. Confusion for changing Xor in XNor and P in notP.
ALU carry prop: the gate computing carry received wrong inputs (from left P and G instead of right). Confusion mainly due to the wrong order of bits in Mesa.
Boolean equation for ALU opcode were wrong (And instead of Or).
Root of the carry prop tree was miswired in the code. Simple typo. CarryOut was only connected to gates. Could have been caught by a static checker.