DragOps.slides
February 27, 1984
Execution Unit Features
8 160  32-bit registers
0 128 registers used to cache local variables
0 16 registers used for runtime
0 12 registers used for constants
0 4 special registers
0 read two, write one every cycle
8 1 operation per cycle
0 32-bit ALU operation
0 32 _ 32 x 32 shift/extract/insert
0 2 bit multiply step
0 1 bit divide step
0 bypassing avoids waits for register update
8 1 cache read/write per cycle
Instruction Fetch Unit
8 IFU translates DragOps to EU control signals
0 DragOps = interface between IFU and compiler
0 IFU selects registers & operations for EU
0 IFU passes literals to EU
0 IFU gets some data from EU
8 IFU overlaps instruction fetch with EU operations
8 IFU performs control transfers
0 jumps (conditional & unconditional)
0 traps/calls/returns
0 faults
8 IFU controls local frame model
0 S is index to top of stack
0 L is index to base of local frame
0 PC, L saved at call, restored at return
0 S, L adjusted in IFU only
Instruction Set Issues
8 IFU issues
0 IFU has very little space
0 no microcode (PLA, not ROM)
0 simple instructions necessary
0 DragOps should closely match EU
8 compiler issues
0 density worthwhile, but efficiency worth more
0 should have minimal "funny restrictions"
0 must be sufficient for efficient Mesa
Kinds of instructions
8 instructions can be 1, 2, 3, or 5 bytes long
8 RR format - 3 operand arithmetic / logical
0 each operand designates one of
1 16 local registers
1 16 auxilliary registers
1 12 "constant" registers
1 4 stack options
2 source: [S], [S]-, [S-1], [S-1]-
2 destination: [S], [S-1], [S+1]+
8 RJB format - conditional jumps
0 each compares two operands
1 one operand must be on stack
1 other operand is as in RR format
0 each has two opcodes
1 sense of jump is predicted
0 range is [pc-128..pc+127] bytes
More kinds of instructions
8 calls / returns
0 must be fast & simple
0 return PC and L cached in IFU
0 arguments become locals of called frame
1 returns passed back on stack
1 must adjust L at entry, S at exit
0 can directly call 32-bit byte PC
0 can call through [S]
0 global frame not part of call/return
1 G is loaded by separate op
8 reads / writes
0 stack & register versions
0 most have 1 byte offsets
Even more kinds of instructions
8 compact versions
0 stack oriented versions of add, sub
1 can add/sub literals as well
0 stack oriented versions of shifter ops
0 stack <-> register operations
0 1, 2, 4 byte literals
8 others
0 S & L adjusting operations
0 read/write special IFU/EU registers
0 bounds check
0 jumps, noops, traps
0 map operations
0 conditional store
Conditional Store
8 sample _ CStore[ptr, old, new]
0 sample _ ptr^     {hold the bus}
0 IF sample = old THEN ptr^ _ new
8 sources of atomicity
0 CStore
0 cause interrupt
0 enable/disable interrupts (1 processor)
8 capabilities
0 spin locks
0 monitor locks
0 condition variables
0 atomic x _ f[x]
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