[_CD6_]<chipndale>5.2>PWPLA20>PWPLADoc.tioga!1

PWPLADoc.tioga

Created by Louis Monier, March 6, 1985 8:57:08 am PST

Last Edited by: Monier, March 11, 1985 9:48:51 am PST

Last Edited by: Serlet, May 2, 1985 2:21:34 pm PDT

HOW TO USE PWPLA

CEDAR 5.2 — FOR INTERNAL XEROX USE ONLY

PWPLA: Generating PLAs Using PatchWork

Louis Monier

Abstract: PWPLA is a PLA generator. It uses a library of cells, a set of user-defined parameters including a truth-table, and generates PLAs with the help of PatchWork. It can be used interactively from ChipnDale. Its procedural interface make it also easy to call from any user program.

PWPLA: Generating PLAs Using PatchWork: Contents

0. Introduction

1. The library

2. The Truth Table

3. Options

4. Becoming a user

[If you are reading this document on-line, try using the Tioga Levels menus (if you can) to initially browse the top few levels of its structure before reading it straight through.]

XEROX Xerox Corporation
Palo Alto Research Center
3333 Coyote Hill Road
Palo Alto, California 94304
For Internal Xerox Use Only

0. Introduction

This PLA generator is heavily inspired by Bob Mayo's work (Parquet and MakePLA), but relies on PatchWork for making the actual cell assembly. You can use it interactively, as described in section 4, or access it through its procedural interface from another program. You can thus call it from a PW program to generate a PLA to be incorporated automatically in a larger design.

1. The library

PWPLA uses a standard set of cells for building the PLA. At least one such library exists at this moment that implements CMOS self-timed precharged PLAs, i.e. the type we'll use in the Dragon chips. This library comes with the df-file. If you plan to build (and share, I hope) your library of cells, these are the guidelines.

Names of Cells: The names are standard, please stick to them. A number of cells are mandatory, the others are needed only if you want to make use of symetries between pairs of adjacent rows/columns, or if you want to insert extra ground lines.

InterestRect: Adjust the InterestRect (bounding box) of the cells using the appropriate CD command (P-Middle) so that all cells abut perfectly in any configuration. The best way to check that is to assemble your cells in a small PLA and select everything (Space-Right).

Design Name: When PWPLA reads in a library, it appends the design name of the library to the cell name to avoid conflicts if several libraries coexist in the same design. This means that it is a good idea to give a meaningful name to your library, something like "cMOS self-timed PLA library". Don't be shy, it is only a rope. It is also a very good idea to use the comment property of the design to list the particularities of your library.

2. The Truth Table and Boolean Equations

You can specify the content of your PLA with a truth table, or a set of boolean equations that uses the input and output names listed under the "Input" and "Outputs" options. If you provide a dump file name, you can get the truth table corresponding to your set of equations.

The truth table is specified in "Berkeley format", i.e. something like

01010101 | 10001000

01000101 | 10011000

01110101 | 11101100

01000101 | 00001010

00010101 | 00100000

01-00101 | 10101001

On the left side is the AND plane, where every column represent an input; on the rigth side the OR plane and the outputs. The rows are of course product terms.

This format is not too smart, and we'll probably evolve towards something that incorporates the inputs and outputs names and types.

Boolean equations use only three operators: AND, OR and ~ (i.e. NOT). We all know that this is more than enough. You can also use parentheses and end up each equation with a semi-colon.

3. Options

The PLA description is a file that contains the following options. Most of them are similar to Mayo's module generator description. Here is an example.

TileSet ← "/Ivy/Monier/PLA/SelfTimePLATileSet.dale"; -- Required

Says where to get the tiles for the PLA.

TruthTableFile ← "///MyFavoritePLA.tt"; -- Required if no equations

Get the PLA description from a truth table in this file, instead of looking for boolean equations.

Inputs ← LIST["A", "reset", "in9"]; -- Both Required

Outputs ← LIST["out1", "busCmd3"];

Names of the input and outputsignals to the PLA.

out1 = (A AND reset AND in9) OR (~reset AND ~in9); -- Required if no truth table

busCmd3 = (reset AND A) OR ~in9;

Optimize ← TRUE; -- Optional

Run the description through a PLA optimizer. Default is FALSE.

Extras ← 4; -- Optional

How often to place extra ground lines (rows and columns in both planes). Default is a very large number. Equivalent to: ExtraRows ← ExtraColumns ← 4;

ExtraRows ← 12; -- Optional

Sets the spacing of extra ground rows without affecting the number of extra columns.

ExtraColumns ← 8; -- Optional

Sets the spacing of extra ground columns without affecting the number of extra rows. Equivalent to: ExtraAndColumns ← ExtraOrColumns ← 8;

ExtraAndColumns ← 12; -- Optional

Sets the spacing of extra ground columns in the AND plane only.

ExtraOrColumns ← 12; -- Optional

Sets the spacing of extra ground columns in the OR plane only.

TruthTableDumpFile ← "///Dump.tt"; -- Optional

Write a truth table file representing the PLA exactly as layed out, including optimization. Default is NIL, in which case no write is performed.

PrintRows ← 10; -- Optional

If the PLA contains more than this many rows then prints the sequence of natural numbers, which in addition of being educative, lets the user know that something is going on. Every number represent one product term (row). Default is a large number.

4. Becoming a user

First bringover [indigo]<chipndale>5.2>top>pwpla20.df; PWPLA uses CD20 and Cedar 5.2. Look in your profile for the line describing the TIP table for ChipnDale, and add PW.TIP. My entry looks like this:

Chipndale.CMos.TIP: PW.TIP Default

Now to start PWPLA, issue the command

% runPWPLA

after running Chipndale.

Space-U calls the PW menu, and "Run Make PLA generator" should be available. The PLA generator package comes with a complete example including

PLAExample.pla -- the PLA decription

PLAExample.tt -- its truth table

SelfTimePLATileSet.dale -- a set of tiles

So just try it. Click the command "Run Make PLA generator", provide the file name PLAExample.pla and you should get a small PLA, free for the taking. Expect a few seconds for a small PLA, and up to two minutes for a large guy like the IFU PhB PLA, which has a hundred inputs+outputs and almost 300 minterms. Of course, using the optimizer will severely increase the response time. Speaking of optimizers, the one in use now is Mayo's version. Don Curry has another one that relies on knowledge of the types of fields, and apparently can perform better. It might become another option.

5. Plugging into PWPLA

The interface PWPLA provides the type PLADescription and a set of procedures. Unless you plan to build your own PLA-oid generator, you really just need CreatePLAFromFile and CreatePLA. Comments in the interface should suffice.