BeginTop
TRUE

BeginCTG
95 	--Number of channels
34 61	--Horzontal & Vertical channel name counters
h1	hor 0 5
h2	hor 1222 5
h3	hor 1128 5
h4	hor 376 5
h5	hor 188 5
h6	hor 94 5
h7	hor 752 5
h8	hor 94 5
h9	hor 188 5
h10	hor 470 5
h11	hor 752 5
h12	hor 1034 5
h13	hor 564 5
h14	hor 846 5
h15	hor 564 5
h16	hor 752 5
h17	hor 470 5
h18	hor 376 5
h19	hor 470 5
h20	hor 282 5
h21	hor 564 5
h22	hor 658 5
h23	hor 282 5
h24	hor 376 5
h25	hor 470 5
h26	hor 282 5
h27	hor 470 5
h28	hor 846 5
h29	hor 940 5
h30	hor 282 5
h31	hor 564 5
h32	hor 658 5
h33	hor 658 5
h34	hor 658 5
v1	ver 0 5
v2	ver 4190 5
v3	ver 52 5
v4	ver 280 5
v5	ver 4086 5
v6	ver 104 5
v7	ver 464 5
v8	ver 404 5
v9	ver 4138 5
v10	ver 156 5
v11	ver 554 5
v12	ver 2334 5
v13	ver 614 5
v14	ver 1348 5
v15	ver 4034 5
v16	ver 666 5
v17	ver 1432 5
v18	ver 1390 5
v19	ver 2194 5
v20	ver 742 5
v21	ver 1556 5
v22	ver 1914 5
v23	ver 794 5
v24	ver 1224 5
v25	ver 1598 5
v26	ver 2054 5
v27	ver 854 5
v28	ver 896 5
v29	ver 1722 5
v30	ver 938 5
v31	ver 1182 5
v32	ver 1862 5
v33	ver 1140 5
v34	ver 980 5
v35	ver 1080 5
v36	ver 2392 5
v37	ver 2516 5
v38	ver 2392 5
v39	ver 3852 5
v40	ver 3992 5
v41	ver 2450 5
v42	ver 2574 5
v43	ver 2574 5
v44	ver 2698 5
v45	ver 2740 5
v46	ver 3068 5
v47	ver 2864 5
v48	ver 2822 5
v49	ver 2946 5
v50	ver 2906 5
v51	ver 2948 5
v52	ver 3732 5
v53	ver 3072 5
v54	ver 3476 5
v55	ver 3192 5
v56	ver 3596 5
v57	ver 3690 5
v58	ver 3648 5
v59	ver 3248 5
v60	ver 3352 5
v61	ver 3300 5
h1	 v1 1 v2 1 () ( v3 1 v6 1 v10 1 v4 1 v8 1 v7 1 v11 1 v13 1 v16 1 v20 1 v23 1 v27 1 v28 1 v30 1 v34 1 v35 1 v33 1 v31 1 v24 1 v14 1 v18 1 v17 1 v21 1 v25 1 v29 1 v32 1 v22 1 v26 1 v19 1 v12 1 v43 1 v44 1 v39 1 v40 1 v15 1 v5 1 v9 1)
h2	 v1 -1 v2 -1 () ()
h3	 v1 0 v2 0 ( v3 -1 v6 -1 v10 -1 v4 -1 v8 -1 v7 -1 v11 -1 v13 -1 v16 -1 v20 -1 v23 -1 v27 -1 v28 -1 v30 -1 v34 -1 v35 -1 v33 -1 v31 -1 v24 -1 v14 -1 v18 -1 v17 -1 v21 -1 v25 -1 v29 -1 v32 -1 v22 -1 v26 -1 v19 -1 v12 -1 v36 -1 v37 -1 v15 -1 v5 -1 v9 -1) ()
h4	 v12 0 v41 0 ( v38 -1) ( v36 1)
h5	 v12 0 v43 0 () ( v38 1 v41 1)
h6	 v44 0 v39 0 () ()
h7	 v42 0 v45 0 ( v44 -1) ()
h8	 v12 0 v43 0 () ()
h9	 v44 0 v39 0 () ( v48 1 v49 1 v46 1)
h10	 v47 0 v46 0 () ( v50 1 v51 1)
h11	 v36 0 v42 0 ( v41 -1) ( v37 1)
h12	 v37 0 v15 0 ( v42 -1 v45 -1 v47 -1 v50 -1 v51 -1 v52 -1 v39 -1 v40 -1) ()
h13	 v45 0 v47 0 () ()
h14	 v42 0 v45 0 () ()
h15	 v51 0 v39 0 ( v46 -1) ( v53 1 v55 1 v59 1 v54 1 v56 1 v58 1 v57 1 v52 1)
h16	 v51 0 v52 0 ( v53 -1 v55 -1 v59 -1 v61 -1 v60 -1 v54 -1 v56 -1 v58 -1 v57 -1) ()
h17	 v41 0 v44 0 ( v43 -1) ( v42 1)
h18	 v48 0 v46 0 ( v49 -1) ( v47 1)
h19	 v44 0 v47 0 ( v48 -1) ( v45 1)
h20	 v41 0 v43 0 () ()
h21	 v42 0 v44 0 () ()
h22	 v42 0 v44 0 () ()
h23	 v12 0 v38 0 () ()
h24	 v41 0 v43 0 () ()
h25	 v12 0 v36 0 () ()
h26	 v44 0 v48 0 () ()
h27	 v36 0 v41 0 () ()
h28	 v37 0 v42 0 () ()
h29	 v37 0 v42 0 () ()
h30	 v48 0 v49 0 () ()
h31	 v36 0 v41 0 () ()
h32	 v36 0 v41 0 () ()
h33	 v59 0 v54 0 () ( v61 1 v60 1)
h34	 v55 0 v59 0 () ()
v1	 h1 1 h2 1 () ( h3 1)
v2	 h1 -1 h2 -1 ( h3 -1) ()
v3	 h1 0 h3 0 () ()
v4	 h1 0 h3 0 () ()
v5	 h1 0 h3 0 () ()
v6	 h1 0 h3 0 () ()
v7	 h1 0 h3 0 () ()
v8	 h1 0 h3 0 () ()
v9	 h1 0 h3 0 () ()
v10	 h1 0 h3 0 () ()
v11	 h1 0 h3 0 () ()
v12	 h1 0 h3 0 () ( h8 1 h5 1 h23 1 h4 1 h25 1)
v13	 h1 0 h3 0 () ()
v14	 h1 0 h3 0 () ()
v15	 h1 0 h3 0 ( h12 -1) ()
v16	 h1 0 h3 0 () ()
v17	 h1 0 h3 0 () ()
v18	 h1 0 h3 0 () ()
v19	 h1 0 h3 0 () ()
v20	 h1 0 h3 0 () ()
v21	 h1 0 h3 0 () ()
v22	 h1 0 h3 0 () ()
v23	 h1 0 h3 0 () ()
v24	 h1 0 h3 0 () ()
v25	 h1 0 h3 0 () ()
v26	 h1 0 h3 0 () ()
v27	 h1 0 h3 0 () ()
v28	 h1 0 h3 0 () ()
v29	 h1 0 h3 0 () ()
v30	 h1 0 h3 0 () ()
v31	 h1 0 h3 0 () ()
v32	 h1 0 h3 0 () ()
v33	 h1 0 h3 0 () ()
v34	 h1 0 h3 0 () ()
v35	 h1 0 h3 0 () ()
v36	 h4 0 h3 0 ( h25 -1) ( h27 1 h31 1 h32 1 h11 1)
v37	 h11 0 h3 0 () ( h28 1 h29 1 h12 1)
v38	 h5 0 h4 0 ( h23 -1) ()
v39	 h1 0 h12 0 ( h6 -1 h9 -1 h15 -1) ()
v40	 h1 0 h12 0 () ()
v41	 h5 0 h11 0 ( h4 -1 h27 -1 h31 -1 h32 -1) ( h20 1 h24 1 h17 1)
v42	 h17 0 h12 0 ( h11 -1 h28 -1 h29 -1) ( h21 1 h22 1 h7 1 h14 1)
v43	 h1 0 h17 0 ( h8 -1 h5 -1 h20 -1 h24 -1) ()
v44	 h1 0 h7 0 ( h17 -1 h21 -1 h22 -1) ( h6 1 h9 1 h26 1 h19 1)
v45	 h19 0 h12 0 ( h7 -1 h14 -1) ( h13 1)
v46	 h9 0 h15 0 ( h18 -1 h10 -1) ()
v47	 h18 0 h12 0 ( h19 -1 h13 -1) ( h10 1)
v48	 h9 0 h19 0 ( h26 -1) ( h30 1 h18 1)
v49	 h9 0 h18 0 ( h30 -1) ()
v50	 h10 0 h12 0 () ()
v51	 h10 0 h12 0 () ( h15 1 h16 1)
v52	 h15 0 h12 0 ( h16 -1) ()
v53	 h15 0 h16 0 () ()
v54	 h15 0 h16 0 ( h33 -1) ()
v55	 h15 0 h16 0 () ( h34 1)
v56	 h15 0 h16 0 () ()
v57	 h15 0 h16 0 () ()
v58	 h15 0 h16 0 () ()
v59	 h15 0 h16 0 ( h34 -1) ( h33 1)
v60	 h33 0 h16 0 () ()
v61	 h33 0 h16 0 () ()

0 	--Number of external constraints
EndCTG

BeginNetTab

112 	--Number of Nets
tt3: 	{}
nlRq7: 	{}
nRequest3: 	{}
nPreGrant2: 	{}
mcmdt7: 	{}
lRequest5: 	{}
Vdd: 	{}
Shift1: 	{}
S2Out1: 	{}
RqOut2: 	{}
PreGrant1: 	{}
BiasPlus: 	{}
tt4: 	{}
nRequest4: 	{}
nPreGrant3: 	{}
lRequest6: 	{}
dodrt0: 	{}
Shift2: 	{}
S2Out2: 	{}
RqOut3: 	{}
PreGrant2: 	{}
BiasMinus: 	{}
tt5: 	{}
nRequest5: 	{}
nPreGrant4: 	{}
mcmdt9: 	{}
lRequest7: 	{}
dodrt1: 	{}
Shift3: 	{}
S2Out3: 	{}
RqOut4: 	{}
PreGrant3: 	{}
Keep: 	{}
Gnd: 	{}
DoShift: 	{}
DoGrant: 	{}
tt6: 	{}
nRequest6: 	{}
nPreGrant5: 	{}
Shift4: 	{}
S2Out4: 	{}
RqOut5: 	{}
PreGrant4: 	{}
MCmdall: 	{}
tt7: 	{}
nRequest7: 	{}
nPreGrant6: 	{}
dodrt3: 	{}
Shift5: 	{}
S2Out5: 	{}
RqOut6: 	{}
PreGrant5: 	{}
Grant0: 	{}
nPreGrant7: 	{}
dodrt4: 	{}
Shift6: 	{}
S2Out6: 	{}
RqOut7: 	{}
PreGrant6: 	{}
Grant1: 	{}
dodrt5: 	{}
Shift7: 	{}
S2Out7: 	{}
PreGrant7: 	{}
Grant2: 	{}
nPhA: 	{}
dodrt6: 	{}
Grant3: 	{}
nPhB: 	{}
dodrt7: 	{}
PhA: 	{}
Grant4: 	{}
PhB: 	{}
Grant5: 	{}
nlRq0: 	{}
mcmdt0: 	{}
Grant6: 	{}
nlRq1: 	{}
nReset: 	{}
mcmdt1: 	{}
Grant7: 	{}
nlRq2: 	{}
mcmdt2: 	{}
lRequest0: 	{}
NoGrant: 	{}
nlRq3: 	{}
mcmdt3: 	{}
lRequest1: 	{}
tt0: 	{}
nlRq4: 	{}
nRequest0: 	{}
lRequest2: 	{}
Reset: 	{}
NoRequest: 	{}
tt1: 	{}
nlRq5: 	{}
nRequest1: 	{}
nPreGrant0: 	{}
mcmdt5: 	{}
lRequest3: 	{}
RqOut0: 	{}
NewRequest: 	{}
tt2: 	{}
nlRq6: 	{}
nRequest2: 	{}
nPreGrant1: 	{}
mcmdt6: 	{}
lRequest4: 	{}
Shift0: 	{}
S2Out0: 	{}
RqOut1: 	{}
PreGrant0: 	{}
EndNetTab

BeginTypeTab
13 	--Number of CoTypes
TSPGDNmos: {
	shapeInfo: {shape: {(48 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (46 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (46 88) east FALSE} auxInfo: {} }
	  t2: {physicalPins: { (40 2) south FALSE (40 88) north FALSE} auxInfo: {} }
	  t1: {physicalPins: { (28 88) north FALSE (28 2) south FALSE} auxInfo: {} }
	  t3: {physicalPins: { (16 88) north FALSE (16 2) south FALSE} auxInfo: {} }
	  }
	}
InvertingLatch: {
	shapeInfo: {shape: {(96 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (94 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (94 88) east FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (20 2) south FALSE (20 88) north FALSE} auxInfo: {} }
	  D: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (90 88) north FALSE (80 2) south FALSE} auxInfo: {} }
	  nQ: {physicalPins: { (68 88) north FALSE (68 2) south FALSE} auxInfo: {} }
	  }
	}
InvertingLatchWithClear: {
	shapeInfo: {shape: {(110 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (108 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (108 88) east FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (20 2) south FALSE (20 88) north FALSE} auxInfo: {} }
	  Clear: {physicalPins: { (32 2) south FALSE (36 88) north FALSE} auxInfo: {} }
	  nQ: {physicalPins: { (82 2) south FALSE (84 88) north FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (94 2) south FALSE (102 88) north FALSE} auxInfo: {} }
	  D: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
	  }
	}
Inverter: {
	shapeInfo: {shape: {(38 90) } shapeFn: {} restriction: {} }
	pins: {
	  Vdd: {physicalPins: { (2 88) north FALSE (36 88) east FALSE} auxInfo: {} }
	  Gnd: {physicalPins: { (2 2) south FALSE (36 2) south FALSE} auxInfo: {} }
	  in: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
	  out: {physicalPins: { (32 88) north FALSE (32 2) south FALSE} auxInfo: {} }
	  }
	}
NOR: {
	shapeInfo: {shape: {(54 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (52 2) south FALSE (52 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (52 88) east FALSE} auxInfo: {} }
	  in2: {physicalPins: { (20 2) south FALSE (20 88) north FALSE} auxInfo: {} }
	  in1: {physicalPins: { (36 88) north FALSE (36 2) south FALSE} auxInfo: {} }
	  out: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
	  }
	}
TSKNSPassgates: {
	shapeInfo: {shape: {(136 90) } shapeFn: {} restriction: {} }
	pins: {
	  PhB: {physicalPins: { (32 88) north FALSE (52 2) south FALSE} auxInfo: {} }
	  lRequest: {physicalPins: { (52 88) north FALSE (110 2) south FALSE} auxInfo: {} }
	  RqOut: {physicalPins: { (118 88) north FALSE (122 2) south FALSE} auxInfo: {} }
	  NoRequest: {physicalPins: { (128 88) north FALSE (98 2) south FALSE} auxInfo: {} }
	  Gnd: {physicalPins: { (2 2) south FALSE (134 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (134 88) east FALSE (2 88) north FALSE} auxInfo: {} }
	  Grant: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
	  Keep: {physicalPins: { (18 88) north FALSE (18 2) south FALSE} auxInfo: {} }
	  nPhA: {physicalPins: { (74 2) south FALSE} auxInfo: {} }
	  }
	}
InvertingLatchWithPreset: {
	shapeInfo: {shape: {(116 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (114 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (114 88) east FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (104 88) north FALSE (100 2) south FALSE} auxInfo: {} }
	  nPreset: {physicalPins: { (38 88) north FALSE (38 2) south FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (22 88) north FALSE (22 2) south FALSE} auxInfo: {} }
	  D: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
	  nQ: {physicalPins: { (88 2) south FALSE (88 88) north FALSE} auxInfo: {} }
	  }
	}
NAND: {
	shapeInfo: {shape: {(56 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (54 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (54 88) east FALSE} auxInfo: {} }
	  in1: {physicalPins: { (18 88) north FALSE (18 2) south FALSE} auxInfo: {} }
	  in2: {physicalPins: { (34 88) north FALSE (34 2) south FALSE} auxInfo: {} }
	  out: {physicalPins: { (50 88) north FALSE (50 2) south FALSE} auxInfo: {} }
	  }
	}
StaticPrecharge: {
	shapeInfo: {shape: {(52 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (50 88) east FALSE (2 88) north FALSE} auxInfo: {} }
	  out: {physicalPins: { (44 2) south FALSE (46 88) north FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (32 2) south FALSE (32 88) north FALSE} auxInfo: {} }
	  BiasPlus: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
	  }
	}
NonInvertingLatch: {
	shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (118 2) south FALSE (118 2) south FALSE (118 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (118 88) east FALSE (2 88) north FALSE} auxInfo: {} }
	  Q: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
	  D: {physicalPins: { (36 88) north FALSE (36 2) south FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (48 2) south FALSE (48 88) north FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (104 2) south FALSE (110 88) north FALSE} auxInfo: {} }
	  }
	}
DualRailLatch: {
	shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (118 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (118 88) east FALSE} auxInfo: {} }
	  Clock: {physicalPins: { (48 2) south FALSE (48 88) north FALSE} auxInfo: {} }
	  nQ: {physicalPins: { (92 2) south FALSE (92 88) north FALSE} auxInfo: {} }
	  Q: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
	  D: {physicalPins: { (36 2) south FALSE (36 88) north FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (104 2) south FALSE (110 88) north FALSE} auxInfo: {} }
	  }
	}
TSBiasGen: {
	shapeInfo: {shape: {(86 90) } shapeFn: {} restriction: {} }
	pins: {
	  Gnd: {physicalPins: { (2 2) south FALSE (84 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (2 88) north FALSE (84 88) east FALSE} auxInfo: {} }
	  BiasPlus: {physicalPins: { (14 88) north FALSE (8 2) south FALSE} auxInfo: {} }
	  BiasMinus: {physicalPins: { (78 88) north FALSE (66 2) south FALSE} auxInfo: {} }
	  }
	}
OAI: {
	shapeInfo: {shape: {(72 90) } shapeFn: {} restriction: {} }
	pins: {
	  ino1: {physicalPins: { (56 2) south FALSE (56 88) north FALSE} auxInfo: {} }
	  ino2: {physicalPins: { (40 2) south FALSE (40 88) north FALSE} auxInfo: {} }
	  ina1: {physicalPins: { (24 2) south FALSE (24 88) north FALSE} auxInfo: {} }
	  out: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
	  }
	}
EndTypeTab

BeginPortTab

52 	--Number of Ports
nRequest3:	NIL "nRequest3" ()
Shift1:	NIL "Shift1" ()
RqOut2:	NIL "RqOut2" ()
S2Out1:	NIL "S2Out1" ()
Vdd:	NIL "Vdd" ()
BiasPlus:	NIL "BiasPlus" ()
nRequest4:	NIL "nRequest4" ()
Shift2:	NIL "Shift2" ()
RqOut3:	NIL "RqOut3" ()
S2Out2:	NIL "S2Out2" ()
BiasMinus:	NIL "BiasMinus" ()
nRequest5:	NIL "nRequest5" ()
Shift3:	NIL "Shift3" ()
RqOut4:	NIL "RqOut4" ()
S2Out3:	NIL "S2Out3" ()
Gnd:	NIL "Gnd" ()
nRequest6:	NIL "nRequest6" ()
Shift4:	NIL "Shift4" ()
RqOut5:	NIL "RqOut5" ()
S2Out4:	NIL "S2Out4" ()
MCmdall:	NIL "MCmdall" ()
nRequest7:	NIL "nRequest7" ()
Grant0:	NIL "Grant0" ()
Shift5:	NIL "Shift5" ()
RqOut6:	NIL "RqOut6" ()
S2Out5:	NIL "S2Out5" ()
Grant1:	NIL "Grant1" ()
Shift6:	NIL "Shift6" ()
RqOut7:	NIL "RqOut7" ()
S2Out6:	NIL "S2Out6" ()
Grant2:	NIL "Grant2" ()
Shift7:	NIL "Shift7" ()
S2Out7:	NIL "S2Out7" ()
Grant3:	NIL "Grant3" ()
nPhA:	NIL "nPhA" ()
Grant4:	NIL "Grant4" ()
PhA:	NIL "PhA" ()
nPhB:	NIL "nPhB" ()
Grant5:	NIL "Grant5" ()
PhB:	NIL "PhB" ()
Grant6:	NIL "Grant6" ()
Grant7:	NIL "Grant7" ()
nReset:	NIL "nReset" ()
nRequest0:	NIL "nRequest0" ()
Reset:	NIL "Reset" ()
nRequest1:	NIL "nRequest1" ()
RqOut0:	NIL "RqOut0" ()
NewRequest:	NIL "NewRequest" ()
nRequest2:	NIL "nRequest2" ()
Shift0:	NIL "Shift0" ()
RqOut1:	NIL "RqOut1" ()
S2Out0:	NIL "S2Out0" ()
EndPortTab

BeginCoTab
92 	--Number of components
PGDB5:	 (3250 660) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south TRUE (28 88) north FALSE} t3: "PreGrant5"  { (16 2) south TRUE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north FALSE (40 2) south TRUE}};
		h33 v61 h16 v59 () () () ()
PGDA5:	 (3302 660) TRUE TSPGDNmos 0 { t1: "nlRq5"  { (28 2) south TRUE (28 88) north FALSE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out5"  { (40 88) north FALSE (40 2) south TRUE}};
		h33 v60 h16 v61 () () () ()
DDs1:	 (3194 660) TRUE StaticPrecharge 0 { Clock: "nPhA"  { (32 88) north FALSE (32 2) south TRUE} out: "Keep"  { (46 88) north FALSE (44 2) south TRUE} Vdd: "Vdd"  { (2 88) north TRUE (50 88) east FALSE} Gnd: "Gnd"  { (50 2) south FALSE (50 2) south FALSE (2 2) south TRUE} BiasPlus: "BiasPlus"  { (6 88) north TRUE (6 2) south FALSE}};
		h34 v59 h16 v55 () () () ()
DDl1:	 (3354 660) TRUE NonInvertingLatch 0 { Clock: "PhB"  { (48 88) north FALSE (48 2) south TRUE} D: "dodrt3"  { (36 2) south FALSE (36 88) north TRUE} Q: "dodrt6"  { (8 88) north FALSE (8 2) south TRUE}};
		h33 v54 h16 v60 () () () ()
DDg1:	 (2394 566) TRUE NOR 0 { in1: "Keep"  { (36 2) south TRUE (36 88) north FALSE} in2: "NewRequest"  { (20 88) north TRUE (20 2) south FALSE} out: "dodrt3"  { (8 2) south FALSE (8 88) north TRUE}};
		h31 v41 h32 v36 () () () ()
PGDB6:	 (3196 566) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south TRUE (28 88) north FALSE} t3: "PreGrant6"  { (16 2) south TRUE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north FALSE (40 2) south TRUE}};
		h15 v59 h34 v55 () () () ()
PGDA6:	 (3598 613) TRUE TSPGDNmos 0 { t1: "nlRq6"  { (28 2) south TRUE (28 88) north FALSE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out6"  { (40 88) north FALSE (40 2) south TRUE}};
		h15 v58 h16 v56 () () () ()
DDs2:	 (2395 472) TRUE StaticPrecharge 0 { Clock: "nPhA"  { (32 88) north FALSE (32 2) south TRUE} out: "NoRequest"  { (46 88) north TRUE (44 2) south FALSE} Vdd: "Vdd"  { (2 88) north TRUE (50 88) east FALSE} Gnd: "Gnd"  { (50 2) south FALSE (50 2) south FALSE (2 2) south TRUE} BiasPlus: "BiasPlus"  { (6 88) north TRUE (6 2) south FALSE}};
		h27 v41 h31 v36 () () () ()
DDl2:	 (2824 284) TRUE NonInvertingLatch 0 { Clock: "PhB"  { (48 88) north FALSE (48 2) south TRUE} D: "dodrt5"  { (36 2) south TRUE (36 88) north FALSE} Q: "dodrt7"  { (8 88) north FALSE (8 2) south TRUE}};
		h30 v49 h18 v48 () () () ()
DDi2:	 (3650 613) TRUE Inverter 0 { in: "dodrt1"  { (18 88) north FALSE (18 2) south FALSE} out: "NewRequest"  { (32 2) south FALSE (32 88) north FALSE}};
		h15 v57 h16 v58 () () () ()
DDg2:	 (2518 848) TRUE NOR 0 { in1: "NoRequest"  { (36 2) south TRUE (36 88) north FALSE} in2: "dodrt3"  { (20 88) north FALSE (20 2) south FALSE} out: "dodrt4"  { (8 2) south TRUE (8 88) north FALSE}};
		h28 v42 h29 v37 () () () ()
PGDB7:	 (2521 942) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant7"  { (16 2) south FALSE (16 88) north TRUE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h29 v42 h12 v37 () () () ()
PGDA7:	 (2397 660) TRUE TSPGDNmos 0 { t1: "nlRq7"  { (28 2) south FALSE (28 88) north TRUE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out7"  { (40 88) north TRUE (40 2) south FALSE}};
		h32 v41 h11 v36 () () () ()
DualRL0:	 (2700 331) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt0"  { (36 88) north TRUE (36 2) south FALSE} Q: "nPreGrant0"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant0"  { (92 88) north TRUE (92 2) south FALSE}};
		h26 v48 h19 v44 () () () ()
DDi3:	 (3692 613) TRUE Inverter 0 { in: "dodrt4"  { (18 88) north FALSE (18 2) south FALSE} out: "dodrt5"  { (32 2) south FALSE (32 88) north FALSE}};
		h15 v52 h16 v57 () () () ()
DDg3:	 (2336 378) TRUE NOR 0 { in1: "dodrt6"  { (36 2) south FALSE (36 88) north FALSE} in2: "nPhA"  { (20 88) north TRUE (20 2) south FALSE} out: "DoGrant"  { (8 2) south TRUE (8 88) north FALSE}};
		h4 v36 h25 v12 () () () ()
DualRL1:	 (2452 284) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt1"  { (36 88) north TRUE (36 2) south FALSE} Q: "nPreGrant1"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant1"  { (92 88) north TRUE (92 2) south FALSE}};
		h20 v43 h24 v41 () () () ()
DDg4:	 (2336 190) TRUE NOR 0 { in1: "dodrt7"  { (36 2) south FALSE (36 88) north FALSE} in2: "nPhA"  { (20 88) north TRUE (20 2) south FALSE} out: "DoShift"  { (8 2) south TRUE (8 88) north FALSE}};
		h5 v38 h23 v12 () () () ()
VLPreB1:	 (3074 613) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant1"  { (6 2) south TRUE (6 88) north FALSE} nQ: "Shift2"  { (88 88) north FALSE (88 2) south FALSE}};
		h15 v55 h16 v53 () () () ()
VLPreA1:	 (3304 566) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant1"  { (6 2) south TRUE (6 88) north FALSE} nQ: "Grant1"  { (88 88) north FALSE (88 2) south TRUE}};
		h15 v54 h33 v59 () () () ()
GDTl1:	 (3478 613) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant0"  { (6 2) south TRUE (6 88) north FALSE} nQ: "Grant0"  { (88 88) north TRUE (88 2) south FALSE}};
		h15 v56 h16 v54 () () () ()
DualRL2:	 (2576 566) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt2"  { (36 88) north TRUE (36 2) south FALSE} Q: "nPreGrant2"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant2"  { (92 88) north TRUE (92 2) south FALSE}};
		h21 v44 h22 v42 () () () ()
VLPreB2:	 (2578 472) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant2"  { (6 2) south TRUE (6 88) north FALSE} nQ: "Shift3"  { (88 88) north FALSE (88 2) south FALSE}};
		h17 v44 h21 v42 () () () ()
VLPreA2:	 (2454 190) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant2"  { (6 2) south FALSE (6 88) north FALSE} nQ: "Grant2"  { (88 88) north FALSE (88 2) south TRUE}};
		h5 v43 h20 v41 () () () ()
INVB0:	 (2700 566) TRUE Inverter 0 { in: "S2Out0"  { (18 88) north FALSE (18 2) south TRUE} out: "tt0"  { (32 2) south FALSE (32 88) north FALSE}};
		h19 v45 h7 v44 () () () ()
INVA0:	 (2824 378) TRUE Inverter 0 { in: "nlRq0"  { (18 88) north FALSE (18 2) south TRUE} out: "lRequest0"  { (32 2) south FALSE (32 88) north TRUE}};
		h18 v47 h19 v48 () () () ()
GDTl2:	 (2457 378) TRUE InvertingLatchWithClear 0 { Clock: "DoShift"  { (20 88) north FALSE (20 2) south TRUE} Clear: "Reset"  { (36 88) north FALSE (32 2) south FALSE} D: "nPreGrant0"  { (8 88) north FALSE (8 2) south FALSE} nQ: "Shift1"  { (84 88) north FALSE (82 2) south FALSE}};
		h24 v43 h17 v41 () () () ()
DualRL3:	 (2950 613) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north FALSE (48 2) south TRUE} D: "tt3"  { (36 88) north FALSE (36 2) south TRUE} Q: "nPreGrant3"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant3"  { (92 88) north FALSE (92 2) south TRUE}};
		h15 v53 h16 v51 () () () ()
VLPreB3:	 (2950 472) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant3"  { (6 2) south FALSE (6 88) north TRUE} nQ: "Shift4"  { (88 88) north FALSE (88 2) south FALSE}};
		h10 v46 h15 v51 () () () ()
VLPreA3:	 (3282 848) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south FALSE (22 88) north TRUE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant3"  { (6 2) south FALSE (6 88) north FALSE} nQ: "Grant3"  { (88 88) north TRUE (88 2) south FALSE}};
		h16 v52 h12 v51 () () () ()
KNS0:	 (2589 754) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south TRUE (32 88) north FALSE} lRequest: "lRequest0"  { (110 2) south FALSE (52 88) north FALSE} Grant: "Grant0"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south TRUE (18 88) north FALSE} NoRequest: "NoRequest"  { (98 2) south TRUE (128 88) north FALSE} RqOut: "RqOut0"  { (122 2) south FALSE (118 88) north FALSE}};
		h7 v45 h14 v42 () () () ()
INVB1:	 (2908 707) TRUE Inverter 0 { in: "S2Out1"  { (18 88) north FALSE (18 2) south TRUE} out: "tt1"  { (32 2) south FALSE (32 88) north FALSE}};
		h10 v51 h12 v50 () () () ()
INVA1:	 (2866 707) TRUE Inverter 0 { in: "nlRq1"  { (18 88) north TRUE (18 2) south FALSE} out: "lRequest1"  { (32 2) south FALSE (32 88) north TRUE}};
		h10 v50 h12 v47 () () () ()
DualRL4:	 (2742 754) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt4"  { (36 88) north TRUE (36 2) south FALSE} Q: "nPreGrant4"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant4"  { (92 88) north TRUE (92 2) south FALSE}};
		h13 v47 h12 v45 () () () ()
VLPreB4:	 (2826 190) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south FALSE (38 88) north TRUE} D: "nPreGrant4"  { (6 2) south TRUE (6 88) north FALSE} nQ: "Shift5"  { (88 88) north FALSE (88 2) south FALSE}};
		h9 v49 h30 v48 () () () ()
VLPreA4:	 (2949 237) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south FALSE (22 88) north TRUE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant4"  { (6 2) south FALSE (6 88) north FALSE} nQ: "Grant4"  { (88 88) north TRUE (88 2) south FALSE}};
		h9 v46 h18 v49 () () () ()
KNS1:	 (2898 378) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south FALSE (32 88) north TRUE} lRequest: "lRequest1"  { (110 2) south FALSE (52 88) north FALSE} Grant: "Grant1"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south FALSE (18 88) north TRUE} NoRequest: "NoRequest"  { (98 2) south TRUE (128 88) north FALSE} RqOut: "RqOut1"  { (122 2) south FALSE (118 88) north FALSE}};
		h18 v46 h10 v47 () () () ()
INVB2:	 (2526 754) TRUE Inverter 0 { in: "S2Out2"  { (18 88) north FALSE (18 2) south TRUE} out: "tt2"  { (32 2) south FALSE (32 88) north FALSE}};
		h11 v42 h28 v37 () () () ()
INVA2:	 (2402 378) TRUE Inverter 0 { in: "nlRq2"  { (18 88) north FALSE (18 2) south TRUE} out: "lRequest2"  { (32 2) south TRUE (32 88) north FALSE}};
		h4 v41 h27 v36 () () () ()
DualRL5:	 (3400 331) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt5"  { (36 88) north FALSE (36 2) south TRUE} Q: "nPreGrant5"  { (8 88) north TRUE (8 2) south FALSE} nQ: "PreGrant5"  { (92 88) north FALSE (92 2) south FALSE}};
		h9 v39 h15 v46 () () () ()
VLPreB5:	 (2702 190) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant5"  { (6 2) south FALSE (6 88) north TRUE} nQ: "Shift6"  { (88 88) north FALSE (88 2) south FALSE}};
		h9 v48 h26 v44 () () () ()
VLPreA5:	 (2744 472) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south FALSE (22 88) north TRUE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant5"  { (6 2) south FALSE (6 88) north FALSE} nQ: "Grant5"  { (88 88) north TRUE (88 2) south FALSE}};
		h19 v47 h13 v45 () () () ()
KNS2:	 (2386 96) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south FALSE (32 88) north TRUE} lRequest: "lRequest2"  { (110 2) south FALSE (52 88) north FALSE} Grant: "Grant2"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south FALSE (18 88) north TRUE} NoRequest: "NoRequest"  { (98 2) south FALSE (128 88) north TRUE} RqOut: "RqOut2"  { (122 2) south FALSE (118 88) north FALSE}};
		h8 v43 h5 v12 () () () ()
INVB3:	 (2617 660) TRUE Inverter 0 { in: "S2Out3"  { (18 88) north TRUE (18 2) south FALSE} out: "tt3"  { (32 2) south FALSE (32 88) north FALSE}};
		h22 v44 h7 v42 () () () ()
INVA3:	 (2638 895) TRUE Inverter 0 { in: "nlRq3"  { (18 88) north TRUE (18 2) south FALSE} out: "lRequest3"  { (32 2) south FALSE (32 88) north TRUE}};
		h14 v45 h12 v42 () () () ()
DualRL6:	 (3215 96) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north TRUE (48 2) south FALSE} D: "tt6"  { (36 88) north TRUE (36 2) south FALSE} Q: "nPreGrant6"  { (8 88) north FALSE (8 2) south TRUE} nQ: "PreGrant6"  { (92 88) north FALSE (92 2) south FALSE}};
		h6 v39 h9 v44 () () () ()
VLPreB6:	 (2578 190) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south FALSE (22 88) north TRUE} nPreset: "nReset"  { (38 2) south FALSE (38 88) north TRUE} D: "nPreGrant6"  { (6 2) south FALSE (6 88) north TRUE} nQ: "Shift7"  { (88 88) north FALSE (88 2) south FALSE}};
		h1 v44 h17 v43 () () () ()
VLPreB15:	 (3217 2) TRUE InvertingLatchWithPreset 0 { Clock: "DoShift"  { (22 2) south FALSE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant7"  { (6 2) south FALSE (6 88) north TRUE} nQ: "Shift0"  { (88 88) north FALSE (88 2) south FALSE}};
		h1 v39 h6 v44 () () () ()
VLPreA6:	 (2454 566) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant6"  { (6 2) south FALSE (6 88) north FALSE} nQ: "Grant6"  { (88 88) north TRUE (88 2) south FALSE}};
		h17 v42 h11 v41 () () () ()
VLPreA15:	 (3734 754) TRUE InvertingLatchWithPreset 0 { Clock: "DoGrant"  { (22 2) south TRUE (22 88) north FALSE} nPreset: "nReset"  { (38 2) south TRUE (38 88) north FALSE} D: "nPreGrant7"  { (6 2) south FALSE (6 88) north TRUE} nQ: "Grant7"  { (88 88) north TRUE (88 2) south FALSE}};
		h15 v39 h12 v52 () () () ()
NVL0:	 (2394 2) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest0"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq0"  { (8 88) north TRUE (8 2) south FALSE}};
		h1 v43 h8 v12 () () () ()
KNS3:	 (3854 472) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south FALSE (32 88) north TRUE} lRequest: "lRequest3"  { (110 2) south FALSE (52 88) north FALSE} Grant: "Grant3"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south FALSE (18 88) north TRUE} NoRequest: "NoRequest"  { (98 2) south TRUE (128 88) north FALSE} RqOut: "RqOut3"  { (122 2) south FALSE (118 88) north FALSE}};
		h1 v40 h12 v39 () () () ()
INVB4:	 (2402 237) TRUE Inverter 0 { in: "S2Out4"  { (18 88) north TRUE (18 2) south FALSE} out: "tt4"  { (32 2) south FALSE (32 88) north FALSE}};
		h5 v41 h4 v38 () () () ()
INVA4:	 (3994 472) TRUE Inverter 0 { in: "nlRq4"  { (18 88) north FALSE (18 2) south TRUE} out: "lRequest4"  { (32 2) south TRUE (32 88) north FALSE}};
		h1 v15 h12 v40 () () () ()
DualRL7:	 (3215 1036) TRUE DualRailLatch 0 { Clock: "PhB"  { (48 88) north FALSE (48 2) south TRUE} D: "tt7"  { (36 88) north FALSE (36 2) south TRUE} Q: "nPreGrant7"  { (8 88) north FALSE (8 2) south FALSE} nQ: "PreGrant7"  { (92 88) north FALSE (92 2) south FALSE}};
		h12 v15 h3 v37 () () () ()
NVL1:	 (2394 895) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north FALSE (48 2) south TRUE} D: "nRequest1"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq1"  { (8 88) north FALSE (8 2) south TRUE}};
		h11 v37 h3 v36 () () () ()
MCDs1:	 (2337 754) TRUE StaticPrecharge 0 { Clock: "nPhB"  { (32 88) north FALSE (32 2) south FALSE} out: "NoGrant"  { (46 88) north FALSE (44 2) south TRUE} Vdd: "Vdd"  { (2 88) north TRUE (50 88) east FALSE} Gnd: "Gnd"  { (50 2) south FALSE (50 2) south FALSE (2 2) south TRUE} BiasPlus: "BiasPlus"  { (6 88) north FALSE (6 2) south TRUE}};
		h25 v36 h3 v12 () () () ()
MCDl1:	 (982 519) TRUE InvertingLatch 0 { Clock: "PhA"  { (20 88) north TRUE (20 2) south FALSE} D: "mcmdt9"  { (8 88) north TRUE (8 2) south FALSE} nQ: "mcmdt1"  { (68 2) south TRUE (68 88) north FALSE}};
		h1 v35 h3 v34 () () () ()
MCDi1:	 (940 519) TRUE Inverter 0 { in: "NoGrant"  { (18 88) north TRUE (18 2) south FALSE} out: "mcmdt9"  { (32 2) south FALSE (32 88) north TRUE}};
		h1 v34 h3 v30 () () () ()
MCDg1:	 (1082 519) TRUE NAND 0 { in1: "mcmdt1"  { (18 2) south TRUE (18 88) north FALSE} in2: "PhB"  { (34 2) south TRUE (34 88) north FALSE} out: "mcmdt2"  { (50 2) south TRUE (50 88) north FALSE}};
		h1 v33 h3 v35 () () () ()
KNS4:	 (1724 519) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south TRUE (32 88) north FALSE} lRequest: "lRequest4"  { (110 2) south FALSE (52 88) north FALSE} Grant: "Grant4"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south TRUE (18 88) north FALSE} NoRequest: "NoRequest"  { (98 2) south FALSE (128 88) north TRUE} RqOut: "RqOut4"  { (122 2) south FALSE (118 88) north FALSE}};
		h1 v32 h3 v29 () () () ()
INVB5:	 (1142 519) TRUE Inverter 0 { in: "S2Out5"  { (18 88) north FALSE (18 2) south FALSE} out: "tt5"  { (32 2) south FALSE (32 88) north FALSE}};
		h1 v31 h3 v33 () () () ()
INVA5:	 (898 519) TRUE Inverter 0 { in: "nlRq5"  { (18 88) north TRUE (18 2) south FALSE} out: "lRequest5"  { (32 2) south FALSE (32 88) north TRUE}};
		h1 v30 h3 v28 () () () ()
NVL2:	 (1600 519) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest2"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq2"  { (8 88) north TRUE (8 2) south FALSE}};
		h1 v29 h3 v25 () () () ()
MCDi2:	 (856 519) TRUE Inverter 0 { in: "PhA"  { (18 88) north TRUE (18 2) south FALSE} out: "mcmdt7"  { (32 2) south TRUE (32 88) north FALSE}};
		h1 v28 h3 v27 () () () ()
MCDg2:	 (796 519) TRUE NAND 0 { in1: "mcmdt2"  { (18 2) south TRUE (18 88) north FALSE} in2: "mcmdt3"  { (34 2) south TRUE (34 88) north FALSE} out: "MCmdall"  { (50 2) south TRUE (50 88) north FALSE}};
		h1 v27 h3 v23 () () () ()
KNS5:	 (1916 519) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south TRUE (32 88) north FALSE} lRequest: "lRequest5"  { (110 2) south FALSE (52 88) north TRUE} Grant: "Grant5"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south TRUE (18 88) north FALSE} NoRequest: "NoRequest"  { (98 2) south FALSE (128 88) north TRUE} RqOut: "RqOut5"  { (122 2) south FALSE (118 88) north FALSE}};
		h1 v26 h3 v22 () () () ()
INVB6:	 (1558 519) TRUE Inverter 0 { in: "S2Out6"  { (18 88) north FALSE (18 2) south FALSE} out: "tt6"  { (32 2) south FALSE (32 88) north FALSE}};
		h1 v25 h3 v21 () () () ()
INVA6:	 (1184 519) TRUE Inverter 0 { in: "nlRq6"  { (18 88) north TRUE (18 2) south FALSE} out: "lRequest6"  { (32 2) south FALSE (32 88) north TRUE}};
		h1 v24 h3 v31 () () () ()
PGDB0:	 (744 519) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant0"  { (16 2) south FALSE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h1 v23 h3 v20 () () () ()
PGDA0:	 (1864 519) TRUE TSPGDNmos 0 { t1: "nlRq0"  { (28 2) south FALSE (28 88) north FALSE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out0"  { (40 88) north FALSE (40 2) south FALSE}};
		h1 v22 h3 v32 () () () ()
NVL3:	 (1434 519) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest3"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq3"  { (8 88) north TRUE (8 2) south FALSE}};
		h1 v21 h3 v17 () () () ()
MCDg3:	 (668 519) TRUE OAI 0 { ino1: "PhA"  { (56 88) north TRUE (56 2) south FALSE} ino2: "mcmdt5"  { (40 88) north FALSE (40 2) south TRUE} ina1: "MCmdall"  { (24 88) north FALSE (24 2) south TRUE} out: "mcmdt3"  { (6 2) south TRUE (6 88) north FALSE}};
		h1 v20 h3 v16 () () () ()
KNS6:	 (2056 519) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south TRUE (32 88) north FALSE} lRequest: "lRequest6"  { (110 2) south FALSE (52 88) north TRUE} Grant: "Grant6"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south TRUE (18 88) north FALSE} NoRequest: "NoRequest"  { (98 2) south FALSE (128 88) north TRUE} RqOut: "RqOut6"  { (122 2) south FALSE (118 88) north FALSE}};
		h1 v19 h3 v26 () () () ()
INVB7:	 (1350 519) TRUE Inverter 0 { in: "S2Out7"  { (18 88) north FALSE (18 2) south FALSE} out: "tt7"  { (32 2) south FALSE (32 88) north FALSE}};
		h1 v18 h3 v14 () () () ()
INVA7:	 (1392 519) TRUE Inverter 0 { in: "nlRq7"  { (18 88) north TRUE (18 2) south FALSE} out: "lRequest7"  { (32 2) south FALSE (32 88) north TRUE}};
		h1 v17 h3 v18 () () () ()
PGDB1:	 (616 519) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant1"  { (16 2) south FALSE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h1 v16 h3 v13 () () () ()
PGDA1:	 (2339 284) TRUE TSPGDNmos 0 { t1: "nlRq1"  { (28 2) south FALSE (28 88) north FALSE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out1"  { (40 88) north FALSE (40 2) south FALSE}};
		h23 v38 h4 v12 () () () ()
NVL4:	 (1226 519) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest4"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq4"  { (8 88) north FALSE (8 2) south TRUE}};
		h1 v14 h3 v24 () () () ()
MCDg4:	 (556 519) TRUE NAND 0 { in1: "mcmdt2"  { (18 2) south TRUE (18 88) north FALSE} in2: "mcmdt6"  { (34 2) south TRUE (34 88) north FALSE} out: "mcmdt5"  { (50 2) south TRUE (50 88) north FALSE}};
		h1 v13 h3 v11 () () () ()
KNS7:	 (2196 519) TRUE TSKNSPassgates 0 { nPhA: "nPhA"  { (74 2) south TRUE} PhB: "PhB"  { (52 2) south TRUE (32 88) north FALSE} lRequest: "lRequest7"  { (110 2) south FALSE (52 88) north TRUE} Grant: "Grant7"  { (6 88) north FALSE (6 2) south FALSE} Keep: "Keep"  { (18 2) south TRUE (18 88) north FALSE} NoRequest: "NoRequest"  { (98 2) south FALSE (128 88) north TRUE} RqOut: "RqOut7"  { (122 2) south FALSE (118 88) north FALSE}};
		h1 v12 h3 v19 () () () ()
bg1:	 (466 519) TRUE TSBiasGen 0 { Vdd: "Vdd"  { (84 88) east TRUE (2 88) north FALSE} Gnd: "Gnd"  { (84 2) south TRUE (2 2) south FALSE} BiasMinus: "BiasMinus"  { (66 2) south FALSE (78 88) north FALSE} BiasPlus: "BiasPlus"  { (8 2) south FALSE (14 88) north TRUE}};
		h1 v11 h3 v7 () () () ()
PGDB2:	 (106 519) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant2"  { (16 2) south FALSE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h1 v10 h3 v6 () () () ()
PGDA2:	 (4088 519) TRUE TSPGDNmos 0 { t1: "nlRq2"  { (28 2) south FALSE (28 88) north TRUE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out2"  { (40 88) north FALSE (40 2) south FALSE}};
		h1 v9 h3 v5 () () () ()
NVL5:	 (282 519) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest5"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq5"  { (8 88) north TRUE (8 2) south FALSE}};
		h1 v8 h3 v4 () () () ()
MCDg5:	 (406 519) TRUE NAND 0 { in1: "mcmdt5"  { (18 2) south TRUE (18 88) north FALSE} in2: "mcmdt7"  { (34 2) south TRUE (34 88) north FALSE} out: "mcmdt6"  { (50 2) south TRUE (50 88) north FALSE}};
		h1 v7 h3 v8 () () () ()
PGDB3:	 (54 519) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant3"  { (16 2) south FALSE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h1 v6 h3 v3 () () () ()
PGDA3:	 (4140 519) TRUE TSPGDNmos 0 { t1: "nlRq3"  { (28 2) south FALSE (28 88) north TRUE} t3: "PhB"  { (16 2) south TRUE (16 88) north FALSE} t2: "S2Out3"  { (40 88) north FALSE (40 2) south FALSE}};
		h1 v2 h3 v9 () () () ()
NVL6:	 (158 519) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north TRUE (48 2) south FALSE} D: "nRequest6"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq6"  { (8 88) north TRUE (8 2) south FALSE}};
		h1 v4 h3 v10 () () () ()
PGDB4:	 (2 519) TRUE TSPGDNmos 0 { t1: "PhA"  { (28 2) south FALSE (28 88) north TRUE} t3: "PreGrant4"  { (16 2) south FALSE (16 88) north FALSE} t2: "NoGrant"  { (40 88) north TRUE (40 2) south FALSE}};
		h1 v3 h3 v1 () () () ()
PGDA4:	 (4036 519) TRUE TSPGDNmos 0 { t1: "nlRq4"  { (28 2) south FALSE (28 88) north TRUE} t3: "PhB"  { (16 2) south FALSE (16 88) north TRUE} t2: "S2Out4"  { (40 88) north FALSE (40 2) south FALSE}};
		h1 v5 h3 v15 () () () ()
NVL7:	 (2035 1130) TRUE NonInvertingLatch 0 { Clock: "PhA"  { (48 88) north FALSE (48 2) south TRUE} D: "nRequest7"  { (36 2) south FALSE (36 88) north FALSE} Q: "nlRq7"  { (8 88) north FALSE (8 2) south TRUE}};
		h3 v2 h2 v1 () () () ()
EndCoTab

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