BeginTop
TRUE

BeginCTG
8 	--Number of channels
4 5	--Horzontal & Vertical channel name counters
h1	hor 0 5
h2	hor 94 5
h4	hor 188 5
v1	ver 0 5
v2	ver 42 5
v3	ver 84 5
v4	ver 126 5
v5	ver 186 5
h1	 v1 1 v5 1 () ( v2 1 v3 1 v4 1)
h2	 v1 0 v2 0 () ()
h4	 v1 -1 v5 -1 ( v2 -1 v3 -1 v4 -1) ()
v1	 h1 1 h4 1 () ( h2 1)
v2	 h1 0 h4 0 ( h2 -1) ()
v3	 h1 0 h4 0 () ()
v4	 h1 0 h4 0 () ()
v5	 h1 -1 h4 -1 () ()

0 	--Number of external constraints
EndCTG

BeginNetTab

15 	--Number of Nets
Vdd: 	{pinNets: { Vdd@PassB Vdd@InvD Vdd@InvC Vdd@InvB Vdd@InvA}}
input[0]: 	{pinNets: { in@InvA}}
input[1]: 	{pinNets: { in@InvB}}
input[2]: 	{pinNets: { in@InvC}}
input[3]: 	{pinNets: { in@InvD}}
Gnd: 	{pinNets: { Gnd@PassB Gnd@InvD Gnd@InvC Gnd@InvB Gnd@InvA}}
clock: 	{pinNets: { in1@PassB}}
output[0]: 	{pinNets: {}}
output[1]: 	{pinNets: { out@PassB}}
output[2]: 	{pinNets: {}}
output[3]: 	{pinNets: {}}
temp[0]: 	{pinNets: { out@InvA}}
temp[1]: 	{pinNets: { in2@PassB out@InvB}}
temp[2]: 	{pinNets: { out@InvC}}
temp[3]: 	{pinNets: { out@InvD}}
EndNetTab

BeginTypeTab
2 	--Number of CoTypes
Inverter: {
	shapeInfo: {shape: {(38 90) sw: (10 50) } shapeFn: {} restriction: {} }
	pins: {
	  out: {physicalPins: { (32 2) south FALSE (32 88) north FALSE} auxInfo: {} }
	  in: {physicalPins: { (18 88) north FALSE (18 2) south FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (10 88) north FALSE} auxInfo: {} }
	  Gnd: {physicalPins: { (12 40) swVer FALSE (36 40) east FALSE} auxInfo: {} }
	  }
	instances: ( InvD InvC InvB InvA)
	}
NAND: {
	shapeInfo: {shape: {(56 90) sw: (12 50) } shapeFn: {} restriction: {} }
	pins: {
	  out: {physicalPins: { (50 2) south FALSE (50 88) north FALSE} auxInfo: {} }
	  in2: {physicalPins: { (34 2) south FALSE (34 88) north FALSE} auxInfo: {} }
	  in1: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
	  Vdd: {physicalPins: { (50 30) east FALSE (50 60) east FALSE} auxInfo: {} }
	  Gnd: {physicalPins: { (2 60) west FALSE (2 80) west FALSE} auxInfo: {} }
	  }
	instances: ( PassD PassC PassB PassA)
	}
EndTypeTab

BeginPortTab

9 	--Number of Ports
input[3]:	"input[3]" "input[3]" ()
input[2]:	"input[2]" "input[2]" ()
input[1]:	"input[1]" "input[1]" ()
input[0]:	"input[0]" "input[0]" ()
clock:	"clock" "clock" ()
output[3]:	"output[3]" "output[3]" ()
output[2]:	"output[2]" "output[2]" ()
output[1]:	"output[1]" "output[1]" ()
output[0]:	"output[0]" "output[0]" ()
EndPortTab

BeginCoTab
8 	--Number of components
InvA:	 (44 49) TRUE Inverter 4 { Gnd: "Gnd"  { (2 50) west FALSE (26 50) neVer FALSE} Vdd: "Vdd"  { (28 2) south FALSE} in: "input[0]"  { (20 88) north FALSE (20 2) south FALSE} out: "temp[0]"  { (6 2) south FALSE (6 88) north FALSE}};
		h1 v3 h4 v2 () () () ()
InvB:	 (86 49) TRUE Inverter 0 { Gnd: "Gnd"  { (36 40) east FALSE (12 40) swVer FALSE} Vdd: "Vdd"  { (10 88) north FALSE} in: "input[1]"  { (18 2) south FALSE (18 88) north FALSE} out: "temp[1]"  { (32 88) north FALSE (32 2) south FALSE}};
		h1 v4 h4 v3 () () () ()
InvC:	 (2 2) TRUE Inverter 0 { Gnd: "Gnd"  { (36 40) east FALSE (12 40) swVer FALSE} Vdd: "Vdd"  { (10 88) north FALSE} in: "input[2]"  { (18 2) south FALSE (18 88) north FALSE} out: "temp[2]"  { (32 88) north FALSE (32 2) south FALSE}};
		h1 v2 h2 v1 () () () ()
InvD:	 (2 96) TRUE Inverter 5 { Gnd: "Gnd"  { (36 50) east FALSE (12 50) nwVer FALSE} Vdd: "Vdd"  { (10 2) south FALSE} in: "input[3]"  { (18 88) north FALSE (18 2) south FALSE} out: "temp[3]"  { (32 2) south FALSE (32 88) north FALSE}};
		h2 v2 h4 v1 () () () ()
PassA:	 (128 2) FALSE NAND 4 { Gnd: "Gnd"  { (54 10) east FALSE (54 30) east FALSE} Vdd: "Vdd"  { (6 30) west FALSE (6 60) west FALSE} out: "output[0]"  { (6 2) south FALSE (6 88) north FALSE} in2: "temp[0]"  { (22 2) south FALSE (22 88) north FALSE} in1: "clock"  { (38 2) south FALSE (38 88) north FALSE}}
PassB:	 (128 49) TRUE NAND 0 { Gnd: "Gnd"  { (2 80) west FALSE (2 60) west FALSE} Vdd: "Vdd"  { (50 60) east FALSE (50 30) east FALSE} out: "output[1]"  { (50 88) north FALSE (50 2) south FALSE} in2: "temp[1]"  { (34 88) north FALSE (34 2) south FALSE} in1: "clock"  { (18 88) north FALSE (18 2) south FALSE}};
		h1 v5 h4 v4 () () () ()
PassC:	 (0 0) FALSE NAND 0 { Gnd: "Gnd"  { (2 80) west FALSE (2 60) west FALSE} Vdd: "Vdd"  { (50 60) east FALSE (50 30) east FALSE} out: "output[2]"  { (50 88) north FALSE (50 2) south FALSE} in2: "temp[2]"  { (34 88) north FALSE (34 2) south FALSE} in1: "clock"  { (18 88) north FALSE (18 2) south FALSE}}
PassD:	 (0 0) FALSE NAND 0 { Gnd: "Gnd"  { (2 80) west FALSE (2 60) west FALSE} Vdd: "Vdd"  { (50 60) east FALSE (50 30) east FALSE} out: "output[3]"  { (50 88) north FALSE (50 2) south FALSE} in2: "temp[3]"  { (34 88) north FALSE (34 2) south FALSE} in1: "clock"  { (18 88) north FALSE (18 2) south FALSE}}
EndCoTab

EndTop