(CellTypeName "TSShouArbiter")
(CreationTime "January 14, 1985 2:52:01 pm PST")
(CreatingUser "myang.pa")
(CreationSite "MilkyWay Sol III USA Xerox PARC ComputerResearch Flasher")
(DerivingProgram "Rosemary Structure Capturer" "1954ef3230f9")
(Ports
 ("nRequest0" (G D) (BIDIR))
 ("nRequest1" (G D) (BIDIR))
 ("nRequest2" (G D) (BIDIR))
 ("nRequest3" (G D) (BIDIR))
 ("nRequest4" (G D) (BIDIR))
 ("nRequest5" (G D) (BIDIR))
 ("nRequest6" (G D) (BIDIR))
 ("nRequest7" (G D) (BIDIR))
 ("Grant0" (G D) (BIDIR))
 ("Grant1" (G D) (BIDIR))
 ("Grant2" (G D) (BIDIR))
 ("Grant3" (G D) (BIDIR))
 ("Grant4" (G D) (BIDIR))
 ("Grant5" (G D) (BIDIR))
 ("Grant6" (G D) (BIDIR))
 ("Grant7" (G D) (BIDIR))
 ("Shift0" (G D) (BIDIR))
 ("Shift1" (G D) (BIDIR))
 ("Shift2" (G D) (BIDIR))
 ("Shift3" (G D) (BIDIR))
 ("Shift4" (G D) (BIDIR))
 ("Shift5" (G D) (BIDIR))
 ("Shift6" (G D) (BIDIR))
 ("Shift7" (G D) (BIDIR))
 ("RqOut0" (G D) (BIDIR))
 ("RqOut1" (G D) (BIDIR))
 ("RqOut2" (G D) (BIDIR))
 ("RqOut3" (G D) (BIDIR))
 ("RqOut4" (G D) (BIDIR))
 ("RqOut5" (G D) (BIDIR))
 ("RqOut6" (G D) (BIDIR))
 ("RqOut7" (G D) (BIDIR))
 ("S2Out0" (G D) (BIDIR))
 ("S2Out1" (G D) (BIDIR))
 ("S2Out2" (G D) (BIDIR))
 ("S2Out3" (G D) (BIDIR))
 ("S2Out4" (G D) (BIDIR))
 ("S2Out5" (G D) (BIDIR))
 ("S2Out6" (G D) (BIDIR))
 ("S2Out7" (G D) (BIDIR))
 ("nReset" (G D) (BIDIR))
 ("Reset" (G D) (BIDIR))
 ("NewRequest" (G D) (BIDIR))
 ("MCmdall" (G D) (BIDIR))
 ("PhA" (G D) (BIDIR))
 ("nPhA" (G D) (BIDIR))
 ("PhB" (G D) (BIDIR))
 ("nPhB" (G D) (BIDIR))
 ("Vdd" (G D) (BIDIR))
 ("Gnd" (G D) (BIDIR))
 ("BiasMinus" (G D) (BIDIR))
 ("BiasPlus" (G D) (BIDIR)))

(PrivateFollows)
(N "BiasMinus" (G D))
(N "BiasPlus" (G D))
(N "DoGrant" (G D))
(N "DoShift" (G D))
(N "Gnd" (G D))
(N "Grant0" (G D))
(N "Grant1" (G D))
(N "Grant2" (G D))
(N "Grant3" (G D))
(N "Grant4" (G D))
(N "Grant5" (G D))
(N "Grant6" (G D))
(N "Grant7" (G D))
(N "Keep" (G D))
(N "MCmdall" (G D))
(N "NewRequest" (G D))
(N "NoGrant" (G D))
(N "NoRequest" (G D))
(N "PhA" (G D))
(N "PhB" (G D))
(N "PreGrant0" (G D))
(N "PreGrant1" (G D))
(N "PreGrant2" (G D))
(N "PreGrant3" (G D))
(N "PreGrant4" (G D))
(N "PreGrant5" (G D))
(N "PreGrant6" (G D))
(N "PreGrant7" (G D))
(N "Reset" (G D))
(N "RqOut0" (G D))
(N "RqOut1" (G D))
(N "RqOut2" (G D))
(N "RqOut3" (G D))
(N "RqOut4" (G D))
(N "RqOut5" (G D))
(N "RqOut6" (G D))
(N "RqOut7" (G D))
(N "S2Out0" (G D))
(N "S2Out1" (G D))
(N "S2Out2" (G D))
(N "S2Out3" (G D))
(N "S2Out4" (G D))
(N "S2Out5" (G D))
(N "S2Out6" (G D))
(N "S2Out7" (G D))
(N "Shift0" (G D))
(N "Shift1" (G D))
(N "Shift2" (G D))
(N "Shift3" (G D))
(N "Shift4" (G D))
(N "Shift5" (G D))
(N "Shift6" (G D))
(N "Shift7" (G D))
(N "Vdd" (G D))
(N "dodrt0" (G D))
(N "dodrt1" (G D))
(N "dodrt3" (G D))
(N "dodrt4" (G D))
(N "dodrt5" (G D))
(N "dodrt6" (G D))
(N "dodrt7" (G D))
(N "lRequest0" (G D))
(N "lRequest1" (G D))
(N "lRequest2" (G D))
(N "lRequest3" (G D))
(N "lRequest4" (G D))
(N "lRequest5" (G D))
(N "lRequest6" (G D))
(N "lRequest7" (G D))
(N "mcmdt0" (G D))
(N "mcmdt1" (G D))
(N "mcmdt2" (G D))
(N "mcmdt3" (G D))
(N "mcmdt5" (G D))
(N "mcmdt6" (G D))
(N "mcmdt7" (G D))
(N "mcmdt9" (G D))
(N "nPhA" (G D))
(N "nPhB" (G D))
(N "nPreGrant0" (G D))
(N "nPreGrant1" (G D))
(N "nPreGrant2" (G D))
(N "nPreGrant3" (G D))
(N "nPreGrant4" (G D))
(N "nPreGrant5" (G D))
(N "nPreGrant6" (G D))
(N "nPreGrant7" (G D))
(N "nRequest0" (G D))
(N "nRequest1" (G D))
(N "nRequest2" (G D))
(N "nRequest3" (G D))
(N "nRequest4" (G D))
(N "nRequest5" (G D))
(N "nRequest6" (G D))
(N "nRequest7" (G D))
(N "nReset" (G D))
(N "nlRq0" (G D))
(N "nlRq1" (G D))
(N "nlRq2" (G D))
(N "nlRq3" (G D))
(N "nlRq4" (G D))
(N "nlRq5" (G D))
(N "nlRq6" (G D))
(N "nlRq7" (G D))
(N "tt0" (G D))
(N "tt1" (G D))
(N "tt2" (G D))
(N "tt3" (G D))
(N "tt4" (G D))
(N "tt5" (G D))
(N "tt6" (G D))
(N "tt7" (G D))
(PN "nRequest0" "nRequest0")
(PN "nRequest1" "nRequest1")
(PN "nRequest2" "nRequest2")
(PN "nRequest3" "nRequest3")
(PN "nRequest4" "nRequest4")
(PN "nRequest5" "nRequest5")
(PN "nRequest6" "nRequest6")
(PN "nRequest7" "nRequest7")
(PN "Grant0" "Grant0")
(PN "Grant1" "Grant1")
(PN "Grant2" "Grant2")
(PN "Grant3" "Grant3")
(PN "Grant4" "Grant4")
(PN "Grant5" "Grant5")
(PN "Grant6" "Grant6")
(PN "Grant7" "Grant7")
(PN "Shift0" "Shift0")
(PN "Shift1" "Shift1")
(PN "Shift2" "Shift2")
(PN "Shift3" "Shift3")
(PN "Shift4" "Shift4")
(PN "Shift5" "Shift5")
(PN "Shift6" "Shift6")
(PN "Shift7" "Shift7")
(PN "RqOut0" "RqOut0")
(PN "RqOut1" "RqOut1")
(PN "RqOut2" "RqOut2")
(PN "RqOut3" "RqOut3")
(PN "RqOut4" "RqOut4")
(PN "RqOut5" "RqOut5")
(PN "RqOut6" "RqOut6")
(PN "RqOut7" "RqOut7")
(PN "S2Out0" "S2Out0")
(PN "S2Out1" "S2Out1")
(PN "S2Out2" "S2Out2")
(PN "S2Out3" "S2Out3")
(PN "S2Out4" "S2Out4")
(PN "S2Out5" "S2Out5")
(PN "S2Out6" "S2Out6")
(PN "S2Out7" "S2Out7")
(PN "nReset" "nReset")
(PN "Reset" "Reset")
(PN "NewRequest" "NewRequest")
(PN "MCmdall" "MCmdall")
(PN "PhA" "PhA")
(PN "nPhA" "nPhA")
(PN "PhB" "PhB")
(PN "nPhB" "nPhB")
(PN "Vdd" "Vdd")
(PN "Gnd" "Gnd")
(PN "BiasMinus" "BiasMinus")
(PN "BiasPlus" "BiasPlus")
(CI "DDg1" "NOR"
 (CIC
  ("in1" "Keep")
  ("in2" "NewRequest")
  ("out" "dodrt3")))
(CI "DDg2" "NOR"
 (CIC
  ("in1" "NoRequest")
  ("in2" "dodrt3")
  ("out" "dodrt4")))
(CI "DDg3" "NOR"
 (CIC
  ("in1" "dodrt6")
  ("in2" "nPhA")
  ("out" "DoGrant")))
(CI "DDg4" "NOR"
 (CIC
  ("in1" "dodrt7")
  ("in2" "nPhA")
  ("out" "DoShift")))
(CI "DDi2" "Inverter"
 (CIC
  ("in" "dodrt1")
  ("out" "NewRequest")))
(CI "DDi3" "Inverter"
 (CIC
  ("in" "dodrt4")
  ("out" "dodrt5")))
(CI "DDl1" "NonInvertingLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "dodrt3")
  ("Q" "dodrt6")))
(CI "DDl2" "NonInvertingLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "dodrt5")
  ("Q" "dodrt7")))
(CI "DDs1" "StaticPrecharge"
 (CIC
  ("Clock" "nPhA")
  ("out" "Keep")
  ("Vdd" "Vdd")
  ("Gnd" "Gnd")
  ("BiasPlus" "BiasPlus")))
(CI "DDs2" "StaticPrecharge"
 (CIC
  ("Clock" "nPhA")
  ("out" "NoRequest")
  ("Vdd" "Vdd")
  ("Gnd" "Gnd")
  ("BiasPlus" "BiasPlus")))
(CI "DualRL0" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt0")
  ("Q" "nPreGrant0")
  ("nQ" "PreGrant0"))
 
 )
(CI "DualRL1" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt1")
  ("Q" "nPreGrant1")
  ("nQ" "PreGrant1"))
 
 )
(CI "DualRL2" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt2")
  ("Q" "nPreGrant2")
  ("nQ" "PreGrant2"))
 
 )
(CI "DualRL3" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt3")
  ("Q" "nPreGrant3")
  ("nQ" "PreGrant3"))
 
 )
(CI "DualRL4" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt4")
  ("Q" "nPreGrant4")
  ("nQ" "PreGrant4"))
 
 )
(CI "DualRL5" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt5")
  ("Q" "nPreGrant5")
  ("nQ" "PreGrant5"))
 
 )
(CI "DualRL6" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt6")
  ("Q" "nPreGrant6")
  ("nQ" "PreGrant6"))
 
 )
(CI "DualRL7" "DualRailLatch"
 (CIC
  ("Clock" "PhB")
  ("D" "tt7")
  ("Q" "nPreGrant7")
  ("nQ" "PreGrant7"))
 
 )
(CI "GDTl1" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant0")
  ("nQ" "Grant0"))
 
 )
(CI "GDTl2" "InvertingLatchWithClear"
 (CIC
  ("Clock" "DoShift")
  ("Clear" "Reset")
  ("D" "nPreGrant0")
  ("nQ" "Shift1"))
 
 )
(CI "INVA0" "Inverter"
 (CIC
  ("in" "nlRq0")
  ("out" "lRequest0"))
 
 )
(CI "INVA1" "Inverter"
 (CIC
  ("in" "nlRq1")
  ("out" "lRequest1"))
 
 )
(CI "INVA2" "Inverter"
 (CIC
  ("in" "nlRq2")
  ("out" "lRequest2"))
 
 )
(CI "INVA3" "Inverter"
 (CIC
  ("in" "nlRq3")
  ("out" "lRequest3"))
 
 )
(CI "INVA4" "Inverter"
 (CIC
  ("in" "nlRq4")
  ("out" "lRequest4"))
 
 )
(CI "INVA5" "Inverter"
 (CIC
  ("in" "nlRq5")
  ("out" "lRequest5"))
 
 )
(CI "INVA6" "Inverter"
 (CIC
  ("in" "nlRq6")
  ("out" "lRequest6"))
 
 )
(CI "INVA7" "Inverter"
 (CIC
  ("in" "nlRq7")
  ("out" "lRequest7"))
 
 )
(CI "INVB0" "Inverter"
 (CIC
  ("in" "S2Out0")
  ("out" "tt0"))
 
 )
(CI "INVB1" "Inverter"
 (CIC
  ("in" "S2Out1")
  ("out" "tt1"))
 
 )
(CI "INVB2" "Inverter"
 (CIC
  ("in" "S2Out2")
  ("out" "tt2"))
 
 )
(CI "INVB3" "Inverter"
 (CIC
  ("in" "S2Out3")
  ("out" "tt3"))
 
 )
(CI "INVB4" "Inverter"
 (CIC
  ("in" "S2Out4")
  ("out" "tt4"))
 
 )
(CI "INVB5" "Inverter"
 (CIC
  ("in" "S2Out5")
  ("out" "tt5"))
 
 )
(CI "INVB6" "Inverter"
 (CIC
  ("in" "S2Out6")
  ("out" "tt6"))
 
 )
(CI "INVB7" "Inverter"
 (CIC
  ("in" "S2Out7")
  ("out" "tt7"))
 
 )
(CI "KNS0" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest0")
  ("Grant" "Grant0")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut0"))
 
 )
(CI "KNS1" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest1")
  ("Grant" "Grant1")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut1"))
 
 )
(CI "KNS2" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest2")
  ("Grant" "Grant2")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut2"))
 
 )
(CI "KNS3" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest3")
  ("Grant" "Grant3")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut3"))
 
 )
(CI "KNS4" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest4")
  ("Grant" "Grant4")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut4"))
 
 )
(CI "KNS5" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest5")
  ("Grant" "Grant5")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut5"))
 
 )
(CI "KNS6" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest6")
  ("Grant" "Grant6")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut6"))
 
 )
(CI "KNS7" "TSKNSPassgates"
 (CIC
  ("nPhA" "nPhA")
  ("PhB" "PhB")
  ("lRequest" "lRequest7")
  ("Grant" "Grant7")
  ("Keep" "Keep")
  ("NoRequest" "NoRequest")
  ("RqOut" "RqOut7"))
 
 )
(CI "MCDg1" "NAND"
 (CIC
  ("in1" "mcmdt1")
  ("in2" "PhB")
  ("out" "mcmdt2")))
(CI "MCDg2" "NAND"
 (CIC
  ("in1" "mcmdt2")
  ("in2" "mcmdt3")
  ("out" "MCmdall")))
(CI "MCDg3" "OAI"
 (CIC
  ("ino1" "PhA")
  ("ino2" "mcmdt5")
  ("ina1" "MCmdall")
  ("out" "mcmdt3")))
(CI "MCDg4" "NAND"
 (CIC
  ("in1" "mcmdt2")
  ("in2" "mcmdt6")
  ("out" "mcmdt5")))
(CI "MCDg5" "NAND"
 (CIC
  ("in1" "mcmdt5")
  ("in2" "mcmdt7")
  ("out" "mcmdt6")))
(CI "MCDi1" "Inverter"
 (CIC
  ("in" "NoGrant")
  ("out" "mcmdt9")))
(CI "MCDi2" "Inverter"
 (CIC
  ("in" "PhA")
  ("out" "mcmdt7")))
(CI "MCDl1" "InvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "mcmdt9")
  ("nQ" "mcmdt1")))
(CI "MCDs1" "StaticPrecharge"
 (CIC
  ("Clock" "nPhB")
  ("out" "NoGrant")
  ("Vdd" "Vdd")
  ("Gnd" "Gnd")
  ("BiasPlus" "BiasPlus")))
(CI "NVL0" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest0")
  ("Q" "nlRq0"))
 
 )
(CI "NVL1" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest1")
  ("Q" "nlRq1"))
 
 )
(CI "NVL2" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest2")
  ("Q" "nlRq2"))
 
 )
(CI "NVL3" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest3")
  ("Q" "nlRq3"))
 
 )
(CI "NVL4" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest4")
  ("Q" "nlRq4"))
 
 )
(CI "NVL5" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest5")
  ("Q" "nlRq5"))
 
 )
(CI "NVL6" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest6")
  ("Q" "nlRq6"))
 
 )
(CI "NVL7" "NonInvertingLatch"
 (CIC
  ("Clock" "PhA")
  ("D" "nRequest7")
  ("Q" "nlRq7"))
 
 )
(CI "PGDA0" "TSPGDNmos"
 (CIC
  ("t1" "nlRq0")
  ("t3" "PhB")
  ("t2" "S2Out0"))
 
 )
(CI "PGDA1" "TSPGDNmos"
 (CIC
  ("t1" "nlRq1")
  ("t3" "PhB")
  ("t2" "S2Out1"))
 
 )
(CI "PGDA2" "TSPGDNmos"
 (CIC
  ("t1" "nlRq2")
  ("t3" "PhB")
  ("t2" "S2Out2"))
 
 )
(CI "PGDA3" "TSPGDNmos"
 (CIC
  ("t1" "nlRq3")
  ("t3" "PhB")
  ("t2" "S2Out3"))
 
 )
(CI "PGDA4" "TSPGDNmos"
 (CIC
  ("t1" "nlRq4")
  ("t3" "PhB")
  ("t2" "S2Out4"))
 
 )
(CI "PGDA5" "TSPGDNmos"
 (CIC
  ("t1" "nlRq5")
  ("t3" "PhB")
  ("t2" "S2Out5"))
 
 )
(CI "PGDA6" "TSPGDNmos"
 (CIC
  ("t1" "nlRq6")
  ("t3" "PhB")
  ("t2" "S2Out6"))
 
 )
(CI "PGDA7" "TSPGDNmos"
 (CIC
  ("t1" "nlRq7")
  ("t3" "PhB")
  ("t2" "S2Out7"))
 
 )
(CI "PGDB0" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant0")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB1" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant1")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB2" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant2")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB3" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant3")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB4" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant4")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB5" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant5")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB6" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant6")
  ("t2" "NoGrant"))
 
 )
(CI "PGDB7" "TSPGDNmos"
 (CIC
  ("t1" "PhA")
  ("t3" "PreGrant7")
  ("t2" "NoGrant"))
 
 )
(CI "VLPreA1" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant1")
  ("nQ" "Grant1"))
 
 )
(CI "VLPreA15" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant7")
  ("nQ" "Grant7"))
 
 )
(CI "VLPreA2" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant2")
  ("nQ" "Grant2"))
 
 )
(CI "VLPreA3" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant3")
  ("nQ" "Grant3"))
 
 )
(CI "VLPreA4" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant4")
  ("nQ" "Grant4"))
 
 )
(CI "VLPreA5" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant5")
  ("nQ" "Grant5"))
 
 )
(CI "VLPreA6" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoGrant")
  ("nPreset" "nReset")
  ("D" "nPreGrant6")
  ("nQ" "Grant6"))
 
 )
(CI "VLPreB1" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant1")
  ("nQ" "Shift2"))
 
 )
(CI "VLPreB15" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant7")
  ("nQ" "Shift0"))
 
 )
(CI "VLPreB2" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant2")
  ("nQ" "Shift3"))
 
 )
(CI "VLPreB3" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant3")
  ("nQ" "Shift4"))
 
 )
(CI "VLPreB4" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant4")
  ("nQ" "Shift5"))
 
 )
(CI "VLPreB5" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant5")
  ("nQ" "Shift6"))
 
 )
(CI "VLPreB6" "InvertingLatchWithPreset"
 (CIC
  ("Clock" "DoShift")
  ("nPreset" "nReset")
  ("D" "nPreGrant6")
  ("nQ" "Shift7"))
 
 )
(CI "bg1" "TSBiasGen"
 (CIC
  ("Vdd" "Vdd")
  ("Gnd" "Gnd")
  ("BiasMinus" "BiasMinus")
  ("BiasPlus" "BiasPlus")))