BeginTop
TRUE
BeginCTG
95 --Number of channels
47 48 --Horzontal & Vertical channel name counters
h1 hor 0 5
h2 hor 1128 5
h3 hor 564 5
h4 hor 282 5
h5 hor 94 5
h6 hor 188 5
h7 hor 188 5
h8 hor 94 5
h9 hor 376 5
h10 hor 376 5
h11 hor 470 5
h12 hor 376 5
h13 hor 846 5
h14 hor 752 5
h15 hor 658 5
h16 hor 752 5
h17 hor 658 5
h18 hor 940 5
h19 hor 846 5
h20 hor 658 5
h21 hor 752 5
h22 hor 658 5
h23 hor 940 5
h24 hor 940 5
h25 hor 564 5
h26 hor 188 5
h27 hor 94 5
h28 hor 376 5
h29 hor 282 5
h30 hor 282 5
h31 hor 282 5
h32 hor 94 5
h33 hor 188 5
h34 hor 470 5
h35 hor 376 5
h36 hor 846 5
h37 hor 658 5
h38 hor 752 5
h39 hor 658 5
h40 hor 1034 5
h41 hor 940 5
h42 hor 1034 5
h43 hor 940 5
h44 hor 846 5
h45 hor 658 5
h46 hor 752 5
h47 hor 940 5
v1 ver 0 5
v2 ver 1236 5
v3 ver 620 5
v4 ver 298 5
v5 ver 240 5
v6 ver 120 5
v7 ver 120 5
v8 ver 422 5
v9 ver 578 5
v10 ver 438 5
v11 ver 364 5
v12 ver 240 5
v13 ver 120 5
v14 ver 292 5
v15 ver 416 5
v16 ver 406 5
v17 ver 226 5
v18 ver 100 5
v19 ver 136 5
v20 ver 60 5
v21 ver 166 5
v22 ver 42 5
v23 ver 402 5
v24 ver 350 5
v25 ver 408 5
v26 ver 366 5
v27 ver 980 5
v28 ver 864 5
v29 ver 744 5
v30 ver 860 5
v31 ver 740 5
v32 ver 672 5
v33 ver 796 5
v34 ver 1146 5
v35 ver 1104 5
v36 ver 1032 5
v37 ver 1104 5
v38 ver 1032 5
v39 ver 956 5
v40 ver 900 5
v41 ver 760 5
v42 ver 740 5
v43 ver 1050 5
v44 ver 998 5
v45 ver 1096 5
v46 ver 1138 5
v47 ver 1080 5
v48 ver 1008 5
h1 v1 1 v2 1 () ( v6 1 v5 1 v4 1 v8 1 v3 1 v29 1 v28 1 v27 1 v35 1 v34 1)
h2 v1 -1 v2 -1 ( v22 -1 v21 -1 v17 -1 v26 -1 v25 -1 v3 -1 v42 -1 v39 -1 v48 -1) ()
h3 v1 0 v3 0 ( v12 -1 v11 -1 v16 -1) ( v18 1 v17 1 v24 1 v23 1)
h4 v1 0 v3 0 ( v7 -1 v4 -1 v10 -1 v9 -1) ( v13 1 v12 1 v14 1 v11 1 v15 1)
h5 v1 0 v4 0 ( v6 -1 v5 -1) ( v7 1)
h6 v1 0 v7 0 () ()
h7 v4 0 v3 0 ( v8 -1) ( v10 1 v9 1)
h8 v4 0 v8 0 () ()
h9 v1 0 v12 0 ( v13 -1) ()
h10 v12 0 v11 0 ( v14 -1) ()
h11 v11 0 v3 0 () ( v16 1)
h12 v11 0 v3 0 ( v15 -1) ()
h13 v1 0 v17 0 ( v18 -1) ( v20 1 v19 1)
h14 v1 0 v18 0 () ()
h15 v1 0 v18 0 () ()
h16 v18 0 v17 0 () ()
h17 v18 0 v17 0 () ()
h18 v1 0 v17 0 ( v20 -1 v19 -1) ( v22 1 v21 1)
h19 v17 0 v3 0 ( v23 -1) ( v26 1 v25 1)
h20 v17 0 v23 0 ( v24 -1) ()
h21 v23 0 v3 0 () ()
h22 v23 0 v3 0 () ()
h23 v17 0 v26 0 () ()
h24 v25 0 v3 0 () ()
h25 v3 0 v2 0 ( v32 -1 v27 -1 v38 -1) ( v41 1 v40 1 v39 1 v44 1 v43 1)
h26 v3 0 v27 0 ( v31 -1 v30 -1) ( v32 1 v33 1)
h27 v3 0 v27 0 ( v29 -1 v28 -1) ( v31 1 v30 1)
h28 v3 0 v32 0 () ()
h29 v3 0 v32 0 () ()
h30 v32 0 v27 0 ( v33 -1) ()
h31 v27 0 v2 0 ( v36 -1) ( v37 1)
h32 v27 0 v2 0 ( v35 -1 v34 -1) ( v36 1)
h33 v27 0 v36 0 () ()
h34 v27 0 v2 0 ( v37 -1) ( v38 1)
h35 v27 0 v37 0 () ()
h36 v3 0 v39 0 ( v40 -1) ( v42 1)
h37 v3 0 v40 0 ( v41 -1) ()
h38 v40 0 v39 0 () ()
h39 v40 0 v39 0 () ()
h40 v3 0 v42 0 () ()
h41 v3 0 v42 0 () ()
h42 v42 0 v39 0 () ()
h43 v42 0 v39 0 () ()
h44 v39 0 v2 0 () ( v47 1 v46 1)
h45 v39 0 v2 0 ( v44 -1 v43 -1) ( v45 1)
h46 v39 0 v2 0 ( v45 -1) ()
h47 v39 0 v2 0 ( v47 -1 v46 -1) ( v48 1)
v1 h1 1 h2 1 () ( h5 1 h6 1 h4 1 h9 1 h3 1 h15 1 h14 1 h13 1 h18 1)
v2 h1 -1 h2 -1 ( h32 -1 h31 -1 h34 -1 h25 -1 h45 -1 h46 -1 h44 -1 h47 -1) ()
v3 h1 0 h2 0 ( h7 -1 h4 -1 h12 -1 h11 -1 h3 -1 h22 -1 h21 -1 h19 -1 h24 -1) ( h27 1 h26 1 h29 1 h28 1 h25 1 h37 1 h36 1 h41 1 h40 1)
v4 h1 0 h4 0 ( h5 -1) ( h8 1 h7 1)
v5 h1 0 h5 0 () ()
v6 h1 0 h5 0 () ()
v7 h5 0 h4 0 ( h6 -1) ()
v8 h1 0 h7 0 ( h8 -1) ()
v9 h7 0 h4 0 () ()
v10 h7 0 h4 0 () ()
v11 h4 0 h3 0 ( h10 -1) ( h12 1 h11 1)
v12 h4 0 h3 0 ( h9 -1) ( h10 1)
v13 h4 0 h9 0 () ()
v14 h4 0 h10 0 () ()
v15 h4 0 h12 0 () ()
v16 h11 0 h3 0 () ()
v17 h3 0 h2 0 ( h17 -1 h16 -1 h13 -1 h18 -1) ( h20 1 h19 1 h23 1)
v18 h3 0 h13 0 ( h15 -1 h14 -1) ( h17 1 h16 1)
v19 h13 0 h18 0 () ()
v20 h13 0 h18 0 () ()
v21 h18 0 h2 0 () ()
v22 h18 0 h2 0 () ()
v23 h3 0 h19 0 ( h20 -1) ( h22 1 h21 1)
v24 h3 0 h20 0 () ()
v25 h19 0 h2 0 () ( h24 1)
v26 h19 0 h2 0 ( h23 -1) ()
v27 h1 0 h25 0 ( h27 -1 h26 -1 h30 -1) ( h32 1 h33 1 h31 1 h35 1 h34 1)
v28 h1 0 h27 0 () ()
v29 h1 0 h27 0 () ()
v30 h27 0 h26 0 () ()
v31 h27 0 h26 0 () ()
v32 h26 0 h25 0 ( h29 -1 h28 -1) ( h30 1)
v33 h26 0 h30 0 () ()
v34 h1 0 h32 0 () ()
v35 h1 0 h32 0 () ()
v36 h32 0 h31 0 ( h33 -1) ()
v37 h31 0 h34 0 ( h35 -1) ()
v38 h34 0 h25 0 () ()
v39 h25 0 h2 0 ( h39 -1 h38 -1 h36 -1 h43 -1 h42 -1) ( h45 1 h46 1 h44 1 h47 1)
v40 h25 0 h36 0 ( h37 -1) ( h39 1 h38 1)
v41 h25 0 h37 0 () ()
v42 h36 0 h2 0 ( h41 -1 h40 -1) ( h43 1 h42 1)
v43 h25 0 h45 0 () ()
v44 h25 0 h45 0 () ()
v45 h45 0 h46 0 () ()
v46 h44 0 h47 0 () ()
v47 h44 0 h47 0 () ()
v48 h47 0 h2 0 () ()
0 --Number of external constraints
EndCTG
BeginNetTab
112 --Number of Nets
BiasPlus: {}
PreGrant1: {}
RqOut2: {}
S2Out1: {}
Shift1: {}
Vdd: {}
lRequest5: {}
mcmdt7: {}
nPreGrant2: {}
nRequest3: {}
nlRq7: {}
tt3: {}
BiasMinus: {}
PreGrant2: {}
RqOut3: {}
S2Out2: {}
Shift2: {}
dodrt0: {}
lRequest6: {}
nPreGrant3: {}
nRequest4: {}
tt4: {}
DoGrant: {}
DoShift: {}
Gnd: {}
Keep: {}
PreGrant3: {}
RqOut4: {}
S2Out3: {}
Shift3: {}
dodrt1: {}
lRequest7: {}
mcmdt9: {}
nPreGrant4: {}
nRequest5: {}
tt5: {}
MCmdall: {}
PreGrant4: {}
RqOut5: {}
S2Out4: {}
Shift4: {}
nPreGrant5: {}
nRequest6: {}
tt6: {}
Grant0: {}
PreGrant5: {}
RqOut6: {}
S2Out5: {}
Shift5: {}
dodrt3: {}
nPreGrant6: {}
nRequest7: {}
tt7: {}
Grant1: {}
PreGrant6: {}
RqOut7: {}
S2Out6: {}
Shift6: {}
dodrt4: {}
nPreGrant7: {}
Grant2: {}
PreGrant7: {}
S2Out7: {}
Shift7: {}
dodrt5: {}
Grant3: {}
dodrt6: {}
nPhA: {}
Grant4: {}
PhA: {}
dodrt7: {}
nPhB: {}
Grant5: {}
PhB: {}
Grant6: {}
mcmdt0: {}
nlRq0: {}
Grant7: {}
mcmdt1: {}
nReset: {}
nlRq1: {}
NoGrant: {}
lRequest0: {}
mcmdt2: {}
nlRq2: {}
lRequest1: {}
mcmdt3: {}
nlRq3: {}
NoRequest: {}
Reset: {}
lRequest2: {}
nRequest0: {}
nlRq4: {}
tt0: {}
NewRequest: {}
RqOut0: {}
lRequest3: {}
mcmdt5: {}
nPreGrant0: {}
nRequest1: {}
nlRq5: {}
tt1: {}
PreGrant0: {}
RqOut1: {}
S2Out0: {}
Shift0: {}
lRequest4: {}
mcmdt6: {}
nPreGrant1: {}
nRequest2: {}
nlRq6: {}
tt2: {}
EndNetTab
BeginTypeTab
13 --Number of CoTypes
InvertingLatch: {
shapeInfo: {shape: {(96 90) } shapeFn: {} restriction: {} }
pins: {
nQ: {physicalPins: { (68 2) south FALSE (68 88) north FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (80 2) south FALSE (90 88) north FALSE} auxInfo: {} }
D: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (94 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (94 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSPGDNmos: {
shapeInfo: {shape: {(48 90) } shapeFn: {} restriction: {} }
pins: {
t3: {physicalPins: { (16 2) south FALSE (16 88) north FALSE} auxInfo: {} }
t1: {physicalPins: { (28 2) south FALSE (28 88) north FALSE} auxInfo: {} }
t2: {physicalPins: { (40 88) north FALSE (40 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (46 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (46 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
InvertingLatchWithClear: {
shapeInfo: {shape: {(110 90) } shapeFn: {} restriction: {} }
pins: {
D: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (102 88) north FALSE (94 2) south FALSE} auxInfo: {} }
nQ: {physicalPins: { (84 88) north FALSE (82 2) south FALSE} auxInfo: {} }
Clear: {physicalPins: { (36 88) north FALSE (32 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (108 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (108 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
NOR: {
shapeInfo: {shape: {(54 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
in1: {physicalPins: { (36 2) south FALSE (36 88) north FALSE} auxInfo: {} }
in2: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (52 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (52 2) south FALSE (52 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
Inverter: {
shapeInfo: {shape: {(38 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (32 2) south FALSE (32 88) north FALSE} auxInfo: {} }
in: {physicalPins: { (18 88) north FALSE (18 2) south FALSE} auxInfo: {} }
Gnd: {physicalPins: { (36 2) south FALSE (2 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (36 88) east FALSE (2 88) north FALSE} auxInfo: {} }
}
}
InvertingLatchWithPreset: {
shapeInfo: {shape: {(116 90) } shapeFn: {} restriction: {} }
pins: {
nQ: {physicalPins: { (88 88) north FALSE (88 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
Clock: {physicalPins: { (22 2) south FALSE (22 88) north FALSE} auxInfo: {} }
nPreset: {physicalPins: { (38 2) south FALSE (38 88) north FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (100 2) south FALSE (104 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (114 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (114 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSKNSPassgates: {
shapeInfo: {shape: {(136 90) } shapeFn: {} restriction: {} }
pins: {
nPhA: {physicalPins: { (74 2) south FALSE} auxInfo: {} }
Keep: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
Grant: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (134 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (134 2) south FALSE (2 2) south FALSE} auxInfo: {} }
NoRequest: {physicalPins: { (98 2) south FALSE (128 88) north FALSE} auxInfo: {} }
RqOut: {physicalPins: { (122 2) south FALSE (118 88) north FALSE} auxInfo: {} }
lRequest: {physicalPins: { (110 2) south FALSE (52 88) north FALSE} auxInfo: {} }
PhB: {physicalPins: { (52 2) south FALSE (32 88) north FALSE} auxInfo: {} }
}
}
NonInvertingLatch: {
shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (110 88) north FALSE (104 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (48 88) north FALSE (48 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (36 2) south FALSE (36 88) north FALSE} auxInfo: {} }
Q: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (118 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (118 2) south FALSE (118 2) south FALSE (118 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
StaticPrecharge: {
shapeInfo: {shape: {(52 90) } shapeFn: {} restriction: {} }
pins: {
BiasPlus: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (32 88) north FALSE (32 2) south FALSE} auxInfo: {} }
out: {physicalPins: { (46 88) north FALSE (44 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (50 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (50 2) south FALSE (50 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
NAND: {
shapeInfo: {shape: {(56 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (50 2) south FALSE (50 88) north FALSE} auxInfo: {} }
in2: {physicalPins: { (34 2) south FALSE (34 88) north FALSE} auxInfo: {} }
in1: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (54 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (54 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
DualRailLatch: {
shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (110 88) north FALSE (104 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (36 88) north FALSE (36 2) south FALSE} auxInfo: {} }
Q: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
nQ: {physicalPins: { (92 88) north FALSE (92 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (48 88) north FALSE (48 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (118 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (118 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSBiasGen: {
shapeInfo: {shape: {(86 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (66 2) south FALSE (78 88) north FALSE} auxInfo: {} }
BiasPlus: {physicalPins: { (8 2) south FALSE (14 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (84 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (84 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
OAI: {
shapeInfo: {shape: {(72 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
ina1: {physicalPins: { (24 88) north FALSE (24 2) south FALSE} auxInfo: {} }
ino2: {physicalPins: { (40 88) north FALSE (40 2) south FALSE} auxInfo: {} }
ino1: {physicalPins: { (56 88) north FALSE (56 2) south FALSE} auxInfo: {} }
}
}
EndTypeTab
BeginPortTab
52 --Number of Ports
BiasPlus: NIL "BiasPlus" ()
Vdd: NIL "Vdd" ()
S2Out1: NIL "S2Out1" ()
RqOut2: NIL "RqOut2" ()
Shift1: NIL "Shift1" ()
nRequest3: NIL "nRequest3" ()
BiasMinus: NIL "BiasMinus" ()
S2Out2: NIL "S2Out2" ()
RqOut3: NIL "RqOut3" ()
Shift2: NIL "Shift2" ()
nRequest4: NIL "nRequest4" ()
Gnd: NIL "Gnd" ()
S2Out3: NIL "S2Out3" ()
RqOut4: NIL "RqOut4" ()
Shift3: NIL "Shift3" ()
nRequest5: NIL "nRequest5" ()
MCmdall: NIL "MCmdall" ()
S2Out4: NIL "S2Out4" ()
RqOut5: NIL "RqOut5" ()
Shift4: NIL "Shift4" ()
nRequest6: NIL "nRequest6" ()
S2Out5: NIL "S2Out5" ()
RqOut6: NIL "RqOut6" ()
Shift5: NIL "Shift5" ()
Grant0: NIL "Grant0" ()
nRequest7: NIL "nRequest7" ()
S2Out6: NIL "S2Out6" ()
RqOut7: NIL "RqOut7" ()
Shift6: NIL "Shift6" ()
Grant1: NIL "Grant1" ()
S2Out7: NIL "S2Out7" ()
Shift7: NIL "Shift7" ()
Grant2: NIL "Grant2" ()
nPhA: NIL "nPhA" ()
Grant3: NIL "Grant3" ()
nPhB: NIL "nPhB" ()
PhA: NIL "PhA" ()
Grant4: NIL "Grant4" ()
PhB: NIL "PhB" ()
Grant5: NIL "Grant5" ()
Grant6: NIL "Grant6" ()
nReset: NIL "nReset" ()
Grant7: NIL "Grant7" ()
Reset: NIL "Reset" ()
nRequest0: NIL "nRequest0" ()
NewRequest: NIL "NewRequest" ()
RqOut0: NIL "RqOut0" ()
nRequest1: NIL "nRequest1" ()
S2Out0: NIL "S2Out0" ()
RqOut1: NIL "RqOut1" ()
Shift0: NIL "Shift0" ()
nRequest2: NIL "nRequest2" ()
EndPortTab
BeginCoTab
184 --Number of components
INVB7*: (0 0) FALSE NIL 0 {}{(73 48) }
INVA6*: (0 0) FALSE NIL 0 {}{(49 68) }
INVB6*: (0 0) FALSE NIL 0 {}{(51 68) }
INVA1*: (0 0) FALSE NIL 0 {}{(36 96) }
INVA4*: (0 0) FALSE NIL 0 {}{(154 23) }
INVB4*: (0 0) FALSE NIL 0 {}{(74 46) }
INVB0*: (0 0) FALSE NIL 0 {}{(32 107) }
INVA2*: (0 0) FALSE NIL 0 {}{(48 73) }
INVA3*: (0 0) FALSE NIL 0 {}{(21 164) }
INVB2*: (0 0) FALSE NIL 0 {}{(84 42) }
INVB5*: (0 0) FALSE NIL 0 {}{(72 48) }
INVA5*: (0 0) FALSE NIL 0 {}{(72 48) }
INVA7*: (0 0) FALSE NIL 0 {}{(69 50) }
INVB3*: (0 0) FALSE NIL 0 {}{(43 80) }
INVA0*: (0 0) FALSE NIL 0 {}{(24 145) }
INVB1*: (0 0) FALSE NIL 0 {}{(109 32) }
DDg1: (1082 848) TRUE NOR 0 { out: "dodrt3" { (8 88) north FALSE (8 2) south FALSE} in2: "NewRequest" { (20 2) south FALSE (20 88) north FALSE} in1: "Keep" { (36 88) north FALSE (36 2) south FALSE}};
h44 v46 h47 v47 () () () ()
DDl1: (958 848) TRUE NonInvertingLatch 0 { Q: "dodrt6" { (8 2) south FALSE (8 88) north FALSE} D: "dodrt3" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h44 v47 h47 v39 () () () ()
DDs1: (485 566) TRUE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "Keep" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhA" { (32 2) south FALSE (32 88) north FALSE}};
h3 v3 h22 v23 () () () ()
PGDA5: (139 566) TRUE TSPGDNmos 0 { t2: "S2Out5" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq5" { (28 88) north FALSE (28 2) south FALSE}};
h3 v17 h17 v18 () () () ()
PGDB5: (904 754) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant5" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h38 v39 h36 v40 () () () ()
KNS6*: (0 0) FALSE NIL 0 {}{(82 150) }
KNS1*: (0 0) FALSE NIL 0 {}{(82 150) }
KNS5*: (0 0) FALSE NIL 0 {}{(93 131) }
KNS4*: (0 0) FALSE NIL 0 {}{(92 131) }
KNS3*: (0 0) FALSE NIL 0 {}{(150 82) }
KNS2*: (0 0) FALSE NIL 0 {}{(150 82) }
KNS7*: (0 0) FALSE NIL 0 {}{(84 145) }
KNS0*: (0 0) FALSE NIL 0 {}{(84 145) }
DDg2: (1069 754) TRUE NOR 0 { out: "dodrt4" { (8 88) north FALSE (8 2) south FALSE} in2: "dodrt3" { (20 2) south FALSE (20 88) north FALSE} in1: "NoRequest" { (36 88) north FALSE (36 2) south FALSE}};
h46 v2 h44 v39 () () () ()
DDi2: (1168 848) TRUE Inverter 0 { out: "NewRequest" { (32 88) north FALSE (32 2) south FALSE} in: "dodrt1" { (18 2) south FALSE (18 88) north FALSE}};
h44 v2 h47 v46 () () () ()
DDl2: (461 49) TRUE NonInvertingLatch 0 { Q: "dodrt7" { (8 2) south FALSE (8 88) north FALSE} D: "dodrt5" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h1 v3 h7 v8 () () () ()
DDs2: (902 660) TRUE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "NoRequest" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhA" { (32 2) south FALSE (32 88) north FALSE}};
h39 v39 h38 v40 () () () ()
PGDA6: (1000 566) TRUE TSPGDNmos 0 { t2: "S2Out6" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq6" { (28 88) north FALSE (28 2) south FALSE}};
h25 v43 h45 v44 () () () ()
PGDB6: (982 190) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant6" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h33 v36 h31 v27 () () () ()
DDg3: (653 1036) TRUE NOR 0 { out: "DoGrant" { (8 88) north FALSE (8 2) south FALSE} in2: "nPhA" { (20 2) south FALSE (20 88) north FALSE} in1: "dodrt6" { (36 88) north FALSE (36 2) south FALSE}};
h40 v42 h2 v3 () () () ()
DDi3: (494 472) TRUE Inverter 0 { out: "dodrt5" { (32 88) north FALSE (32 2) south FALSE} in: "dodrt4" { (18 2) south FALSE (18 88) north FALSE}};
h11 v3 h3 v16 () () () ()
DualRL0: (982 378) TRUE DualRailLatch 0 { nQ: "PreGrant0" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant0" { (8 2) south FALSE (8 88) north FALSE} D: "tt0" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h35 v37 h34 v27 () () () ()
PGDA7: (958 989) TRUE TSPGDNmos 0 { t2: "S2Out7" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq7" { (28 88) north FALSE (28 2) south FALSE}};
h47 v48 h2 v39 () () () ()
PGDB7: (1110 472) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant7" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h34 v2 h25 v38 () () () ()
DDg4: (242 2) TRUE NOR 0 { out: "DoShift" { (8 88) north FALSE (8 2) south FALSE} in2: "nPhA" { (20 2) south FALSE (20 88) north FALSE} in1: "dodrt7" { (36 88) north FALSE (36 2) south FALSE}};
h1 v4 h5 v5 () () () ()
DualRL1: (300 2) TRUE DualRailLatch 0 { nQ: "PreGrant1" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant1" { (8 2) south FALSE (8 88) north FALSE} D: "tt1" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h1 v8 h8 v4 () () () ()
MCDs1*: (0 0) FALSE NIL 0 {}{(72 65) }
NVL6*: (0 0) FALSE NIL 0 {}{(185 59) }
NVL1*: (0 0) FALSE NIL 0 {}{(112 96) }
NVL4*: (0 0) FALSE NIL 0 {}{(77 140) }
NVL0*: (0 0) FALSE NIL 0 {}{(77 140) }
NVL2*: (0 0) FALSE NIL 0 {}{(135 80) }
NVL5*: (0 0) FALSE NIL 0 {}{(101 107) }
MCDi2*: (0 0) FALSE NIL 0 {}{(31 107) }
MCDg5*: (0 0) FALSE NIL 0 {}{(48 107) }
MCDg3*: (0 0) FALSE NIL 0 {}{(71 91) }
MCDg2*: (0 0) FALSE NIL 0 {}{(54 91) }
MCDg4*: (0 0) FALSE NIL 0 {}{(55 91) }
MCDi1*: (0 0) FALSE NIL 0 {}{(108 32) }
MCDl1*: (0 0) FALSE NIL 0 {}{(108 78) }
MCDg1*: (0 0) FALSE NIL 0 {}{(108 46) }
NVL7*: (0 0) FALSE NIL 0 {}{(138 79) }
NVL3*: (0 0) FALSE NIL 0 {}{(97 112) }
DualRL2: (228 566) TRUE DualRailLatch 0 { nQ: "PreGrant2" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant2" { (8 2) south FALSE (8 88) north FALSE} D: "tt2" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h3 v24 h20 v17 () () () ()
GDTl1: (151 143) TRUE InvertingLatchWithPreset 0 { nQ: "Grant0" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant0" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h5 v4 h4 v7 () () () ()
VLPreA1: (2 190) TRUE InvertingLatchWithPreset 0 { nQ: "Grant1" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant1" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h6 v7 h4 v1 () () () ()
VLPreB1: (2 96) TRUE InvertingLatchWithPreset 0 { nQ: "Shift2" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant1" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h5 v7 h6 v1 () () () ()
DualRL3: (60 425) TRUE DualRailLatch 0 { nQ: "PreGrant3" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant3" { (8 2) south FALSE (8 88) north FALSE} D: "tt3" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h9 v12 h3 v1 () () () ()
GDTl2: (1115 331) TRUE InvertingLatchWithClear 0 { nQ: "Shift1" { (82 2) south FALSE (84 88) north FALSE} D: "nPreGrant0" { (8 2) south FALSE (8 88) north FALSE} Clear: "Reset" { (32 2) south FALSE (36 88) north FALSE} Clock: "DoShift" { (20 2) south FALSE (20 88) north FALSE}};
h31 v2 h34 v37 () () () ()
INVA0: (580 190) TRUE Inverter 0 { out: "lRequest0" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq0" { (18 2) south FALSE (18 88) north FALSE}};
h7 v3 h4 v9 () () () ()
INVB0: (903 2) TRUE Inverter 0 { out: "tt0" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out0" { (18 2) south FALSE (18 88) north FALSE}};
h1 v27 h27 v28 () () () ()
VLPreA2: (2 2) TRUE InvertingLatchWithPreset 0 { nQ: "Grant2" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant2" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h1 v6 h5 v1 () () () ()
VLPreB2: (122 2) TRUE InvertingLatchWithPreset 0 { nQ: "Shift3" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant2" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h1 v5 h5 v6 () () () ()
DualRL4: (1074 143) TRUE DualRailLatch 0 { nQ: "PreGrant4" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant4" { (8 2) south FALSE (8 88) north FALSE} D: "tt4" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h32 v2 h31 v36 () () () ()
INVA1: (1106 2) TRUE Inverter 0 { out: "lRequest1" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq1" { (18 2) south FALSE (18 88) north FALSE}};
h1 v34 h32 v35 () () () ()
INVB1: (341 96) TRUE Inverter 0 { out: "tt1" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out1" { (18 2) south FALSE (18 88) north FALSE}};
h8 v8 h7 v4 () () () ()
KNS0: (300 190) TRUE TSKNSPassgates 0 { RqOut: "RqOut0" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant0" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest0" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h7 v10 h4 v4 () () () ()
VLPreA3: (2 284) TRUE InvertingLatchWithPreset 0 { nQ: "Grant3" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant3" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h4 v13 h9 v1 () () () ()
VLPreB3: (122 284) TRUE InvertingLatchWithPreset 0 { nQ: "Shift4" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant3" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h4 v12 h9 v13 () () () ()
PGDA7*: (0 0) FALSE NIL 0 {}{(91 48) }
PGDA6*: (0 0) FALSE NIL 0 {}{(64 68) }
PGDB5*: (0 0) FALSE NIL 0 {}{(72 60) }
PGDB7*: (0 0) FALSE NIL 0 {}{(97 46) }
PGDB0*: (0 0) FALSE NIL 0 {}{(96 46) }
PGDB6*: (0 0) FALSE NIL 0 {}{(85 51) }
PGDB4*: (0 0) FALSE NIL 0 {}{(85 50) }
PGDA1*: (0 0) FALSE NIL 0 {}{(45 96) }
PGDA4*: (0 0) FALSE NIL 0 {}{(74 58) }
PGDA0*: (0 0) FALSE NIL 0 {}{(74 59) }
PGDA2*: (0 0) FALSE NIL 0 {}{(48 91) }
PGDB2*: (0 0) FALSE NIL 0 {}{(39 110) }
PGDA5*: (0 0) FALSE NIL 0 {}{(72 60) }
PGDB1*: (0 0) FALSE NIL 0 {}{(69 63) }
PGDB3*: (0 0) FALSE NIL 0 {}{(69 63) }
PGDA3*: (0 0) FALSE NIL 0 {}{(54 80) }
DualRL5: (788 1036) TRUE DualRailLatch 0 { nQ: "PreGrant5" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant5" { (8 2) south FALSE (8 88) north FALSE} D: "tt5" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h42 v39 h2 v42 () () () ()
INVA2: (495 989) TRUE Inverter 0 { out: "lRequest2" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq2" { (18 2) south FALSE (18 88) north FALSE}};
h24 v3 h2 v25 () () () ()
INVB2: (492 754) TRUE Inverter 0 { out: "tt2" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out2" { (18 2) south FALSE (18 88) north FALSE}};
h21 v3 h19 v23 () () () ()
KNS1: (958 660) TRUE TSKNSPassgates 0 { RqOut: "RqOut1" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant1" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest1" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h45 v45 h46 v39 () () () ()
VLPreA4: (622 942) TRUE InvertingLatchWithPreset 0 { nQ: "Grant4" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant4" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h41 v42 h40 v3 () () () ()
VLPreB4: (622 848) TRUE InvertingLatchWithPreset 0 { nQ: "Shift5" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant4" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h36 v42 h41 v3 () () () ()
bg1*: (0 0) FALSE NIL 0 {}{(84 93) }
DualRL6: (622 2) TRUE DualRailLatch 0 { nQ: "PreGrant6" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant6" { (8 2) south FALSE (8 88) north FALSE} D: "tt6" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h1 v29 h27 v3 () () () ()
INVA3: (368 942) TRUE Inverter 0 { out: "lRequest3" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq3" { (18 2) south FALSE (18 88) north FALSE}};
h19 v25 h2 v26 () () () ()
INVB3: (309 284) TRUE Inverter 0 { out: "tt3" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out3" { (18 2) south FALSE (18 88) north FALSE}};
h4 v11 h10 v14 () () () ()
KNS2: (228 848) TRUE TSKNSPassgates 0 { RqOut: "RqOut2" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant2" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest2" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h19 v26 h23 v17 () () () ()
VLPreA5: (790 942) TRUE InvertingLatchWithPreset 0 { nQ: "Grant5" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant5" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h43 v39 h42 v42 () () () ()
VLPreB5: (790 848) TRUE InvertingLatchWithPreset 0 { nQ: "Shift6" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant5" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h36 v39 h43 v42 () () () ()
DualRL7: (982 284) TRUE DualRailLatch 0 { nQ: "PreGrant7" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant7" { (8 2) south FALSE (8 88) north FALSE} D: "tt7" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}};
h31 v37 h35 v27 () () () ()
INVA4: (807 378) TRUE Inverter 0 { out: "lRequest4" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq4" { (18 2) south FALSE (18 88) north FALSE}};
h30 v27 h25 v32 () () () ()
INVB4: (627 284) TRUE Inverter 0 { out: "tt4" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out4" { (18 2) south FALSE (18 88) north FALSE}};
h29 v32 h28 v3 () () () ()
KNS3: (228 989) TRUE TSKNSPassgates 0 { RqOut: "RqOut3" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant3" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest3" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h23 v26 h2 v17 () () () ()
NVL0: (674 190) TRUE NonInvertingLatch 0 { Q: "nlRq0" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest0" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h26 v33 h30 v32 () () () ()
VLPreA15: (742 96) TRUE InvertingLatchWithPreset 0 { nQ: "Grant7" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant7" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h27 v30 h26 v31 () () () ()
VLPreA6: (862 96) TRUE InvertingLatchWithPreset 0 { nQ: "Grant6" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant6" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}};
h27 v27 h26 v30 () () () ()
VLPreB15: (622 96) TRUE InvertingLatchWithPreset 0 { nQ: "Shift0" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant7" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h27 v31 h26 v3 () () () ()
VLPreB6: (746 2) TRUE InvertingLatchWithPreset 0 { nQ: "Shift7" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant6" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}};
h1 v28 h27 v29 () () () ()
INVA5: (144 754) TRUE Inverter 0 { out: "lRequest5" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq5" { (18 2) south FALSE (18 88) north FALSE}};
h16 v17 h13 v18 () () () ()
INVB5: (144 660) TRUE Inverter 0 { out: "tt5" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out5" { (18 2) south FALSE (18 88) north FALSE}};
h17 v17 h16 v18 () () () ()
KNS4: (622 566) TRUE TSKNSPassgates 0 { RqOut: "RqOut4" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant4" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest4" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h25 v41 h37 v3 () () () ()
MCDg1: (22 754) TRUE NAND 0 { out: "mcmdt2" { (50 88) north FALSE (50 2) south FALSE} in2: "PhB" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt1" { (18 88) north FALSE (18 2) south FALSE}};
h14 v18 h13 v1 () () () ()
MCDi1: (31 660) TRUE Inverter 0 { out: "mcmdt9" { (32 88) north FALSE (32 2) south FALSE} in: "NoGrant" { (18 2) south FALSE (18 88) north FALSE}};
h15 v18 h14 v1 () () () ()
MCDl1: (2 566) TRUE InvertingLatch 0 { nQ: "mcmdt1" { (68 88) north FALSE (68 2) south FALSE} D: "mcmdt9" { (8 2) south FALSE (8 88) north FALSE} Clock: "PhA" { (20 2) south FALSE (20 88) north FALSE}};
h3 v18 h15 v1 () () () ()
MCDs1: (902 566) TRUE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "NoGrant" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhB" { (32 2) south FALSE (32 88) north FALSE}};
h25 v39 h39 v40 () () () ()
NVL1: (982 2) TRUE NonInvertingLatch 0 { Q: "nlRq1" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest1" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h1 v35 h32 v27 () () () ()
DDg1*: (0 0) FALSE NIL 0 {}{(42 117) }
DDl1*: (0 0) FALSE NIL 0 {}{(92 117) }
DDi2*: (0 0) FALSE NIL 0 {}{(30 117) }
DDg2*: (0 0) FALSE NIL 0 {}{(164 30) }
DDg3*: (0 0) FALSE NIL 0 {}{(115 43) }
DDs2*: (0 0) FALSE NIL 0 {}{(72 65) }
DDs1*: (0 0) FALSE NIL 0 {}{(84 55) }
DDi3*: (0 0) FALSE NIL 0 {}{(69 50) }
DDl2*: (0 0) FALSE NIL 0 {}{(83 129) }
DDg4*: (0 0) FALSE NIL 0 {}{(40 123) }
INVA6: (958 566) TRUE Inverter 0 { out: "lRequest6" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq6" { (18 2) south FALSE (18 88) north FALSE}};
h25 v44 h45 v39 () () () ()
INVB6: (1124 566) TRUE Inverter 0 { out: "tt6" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out6" { (18 2) south FALSE (18 88) north FALSE}};
h25 v2 h45 v43 () () () ()
KNS5: (762 566) TRUE TSKNSPassgates 0 { RqOut: "RqOut5" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant5" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest5" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h25 v40 h37 v41 () () () ()
MCDg2: (2 848) TRUE NAND 0 { out: "MCmdall" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt3" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt2" { (18 88) north FALSE (18 2) south FALSE}};
h13 v20 h18 v1 () () () ()
MCDi2: (2 989) TRUE Inverter 0 { out: "mcmdt7" { (32 88) north FALSE (32 2) south FALSE} in: "PhA" { (18 2) south FALSE (18 88) north FALSE}};
h18 v22 h2 v1 () () () ()
NVL2: (254 707) TRUE NonInvertingLatch 0 { Q: "nlRq2" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest2" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h20 v23 h19 v17 () () () ()
INVA7: (366 472) TRUE Inverter 0 { out: "lRequest7" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq7" { (18 2) south FALSE (18 88) north FALSE}};
h11 v16 h3 v11 () () () ()
INVB7: (1103 989) TRUE Inverter 0 { out: "tt7" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out7" { (18 2) south FALSE (18 88) north FALSE}};
h47 v2 h2 v48 () () () ()
KNS6: (1098 660) TRUE TSKNSPassgates 0 { RqOut: "RqOut6" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant6" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest6" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h45 v2 h46 v45 () () () ()
MCDg3: (62 848) TRUE OAI 0 { out: "mcmdt3" { (6 88) north FALSE (6 2) south FALSE} ina1: "MCmdall" { (24 2) south FALSE (24 88) north FALSE} ino2: "mcmdt5" { (40 2) south FALSE (40 88) north FALSE} ino1: "PhA" { (56 2) south FALSE (56 88) north FALSE}};
h13 v19 h18 v20 () () () ()
NVL3: (242 425) TRUE NonInvertingLatch 0 { Q: "nlRq3" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest3" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h10 v11 h3 v12 () () () ()
PGDA0: (622 425) TRUE TSPGDNmos 0 { t2: "S2Out0" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq0" { (28 88) north FALSE (28 2) south FALSE}};
h28 v32 h25 v3 () () () ()
PGDB0: (982 472) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant0" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h34 v38 h25 v27 () () () ()
KNS7: (440 190) TRUE TSKNSPassgates 0 { RqOut: "RqOut7" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant7" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest7" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}};
h7 v9 h4 v10 () () () ()
MCDg4: (153 848) TRUE NAND 0 { out: "mcmdt5" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt6" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt2" { (18 88) north FALSE (18 2) south FALSE}};
h13 v17 h18 v19 () () () ()
NVL4: (828 190) TRUE NonInvertingLatch 0 { Q: "nlRq4" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest4" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h26 v27 h30 v33 () () () ()
PGDA1: (1167 2) TRUE TSPGDNmos 0 { t2: "S2Out1" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq1" { (28 88) north FALSE (28 2) south FALSE}};
h1 v2 h32 v34 () () () ()
PGDB1: (494 284) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant1" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h4 v3 h12 v15 () () () ()
DualRL5*: (0 0) FALSE NIL 0 {}{(142 77) }
DualRL0*: (0 0) FALSE NIL 0 {}{(132 82) }
DualRL7*: (0 0) FALSE NIL 0 {}{(132 82) }
DualRL4*: (0 0) FALSE NIL 0 {}{(108 101) }
DualRL6*: (0 0) FALSE NIL 0 {}{(99 107) }
DualRL2*: (0 0) FALSE NIL 0 {}{(96 110) }
DualRL3*: (0 0) FALSE NIL 0 {}{(164 66) }
DualRL1*: (0 0) FALSE NIL 0 {}{(109 97) }
MCDg5: (168 989) TRUE NAND 0 { out: "mcmdt6" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt7" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt5" { (18 88) north FALSE (18 2) south FALSE}};
h18 v17 h2 v21 () () () ()
NVL5: (44 989) TRUE NonInvertingLatch 0 { Q: "nlRq5" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest5" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h18 v21 h2 v22 () () () ()
PGDA2: (490 848) TRUE TSPGDNmos 0 { t2: "S2Out2" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq2" { (28 88) north FALSE (28 2) south FALSE}};
h19 v3 h24 v25 () () () ()
PGDB2: (352 566) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant2" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h3 v23 h20 v24 () () () ()
bg1: (468 660) TRUE TSBiasGen 0 { BiasPlus: "BiasPlus" { (14 88) north FALSE (8 2) south FALSE} BiasMinus: "BiasMinus" { (78 88) north FALSE (66 2) south FALSE} Gnd: "Gnd" { (2 2) south FALSE (84 2) south FALSE} Vdd: "Vdd" { (2 88) north FALSE (84 88) east FALSE}};
h22 v3 h21 v23 () () () ()
VLPreA5*: (0 0) FALSE NIL 0 {}{(142 73) }
VLPreB5*: (0 0) FALSE NIL 0 {}{(142 73) }
VLPreA4*: (0 0) FALSE NIL 0 {}{(115 90) }
VLPreB4*: (0 0) FALSE NIL 0 {}{(115 90) }
GDTl2*: (0 0) FALSE NIL 0 {}{(61 164) }
VLPreA6*: (0 0) FALSE NIL 0 {}{(76 137) }
VLPreB6*: (0 0) FALSE NIL 0 {}{(97 107) }
VLPreB3*: (0 0) FALSE NIL 0 {}{(82 126) }
VLPreA3*: (0 0) FALSE NIL 0 {}{(82 126) }
VLPreA1*: (0 0) FALSE NIL 0 {}{(138 76) }
VLPreB1*: (0 0) FALSE NIL 0 {}{(138 75) }
GDTl1*: (0 0) FALSE NIL 0 {}{(69 151) }
VLPreB2*: (0 0) FALSE NIL 0 {}{(84 123) }
VLPreA2*: (0 0) FALSE NIL 0 {}{(83 123) }
NVL6: (700 707) TRUE NonInvertingLatch 0 { Q: "nlRq6" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest6" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h37 v40 h36 v3 () () () ()
PGDA3: (242 284) TRUE TSPGDNmos 0 { t2: "S2Out3" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq3" { (28 88) north FALSE (28 2) south FALSE}};
h4 v14 h10 v12 () () () ()
PGDB3: (366 284) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant3" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h4 v15 h12 v11 () () () ()
VLPreA15*: (0 0) FALSE NIL 0 {}{(76 137) }
VLPreB15*: (0 0) FALSE NIL 0 {}{(76 137) }
NVL7: (432 378) TRUE NonInvertingLatch 0 { Q: "nlRq7" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest7" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}};
h12 v3 h11 v11 () () () ()
PGDA4: (622 190) TRUE TSPGDNmos 0 { t2: "S2Out4" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq4" { (28 88) north FALSE (28 2) south FALSE}};
h26 v32 h29 v3 () () () ()
PGDB4: (982 96) TRUE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant4" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}};
h32 v36 h33 v27 () () () ()
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