BeginTop
FALSE
BeginCTG
0 --Number of channels
0 0 --Horzontal & Vertical channel name counters
0 --Number of external constraints
EndCTG
BeginNetTab
112 --Number of Nets
BiasPlus: {}
PreGrant1: {}
RqOut2: {}
S2Out1: {}
Shift1: {}
Vdd: {}
lRequest5: {}
mcmdt7: {}
nPreGrant2: {}
nRequest3: {}
nlRq7: {}
tt3: {}
BiasMinus: {}
PreGrant2: {}
RqOut3: {}
S2Out2: {}
Shift2: {}
dodrt0: {}
lRequest6: {}
nPreGrant3: {}
nRequest4: {}
tt4: {}
DoGrant: {}
DoShift: {}
Gnd: {}
Keep: {}
PreGrant3: {}
RqOut4: {}
S2Out3: {}
Shift3: {}
dodrt1: {}
lRequest7: {}
mcmdt9: {}
nPreGrant4: {}
nRequest5: {}
tt5: {}
MCmdall: {}
PreGrant4: {}
RqOut5: {}
S2Out4: {}
Shift4: {}
nPreGrant5: {}
nRequest6: {}
tt6: {}
Grant0: {}
PreGrant5: {}
RqOut6: {}
S2Out5: {}
Shift5: {}
dodrt3: {}
nPreGrant6: {}
nRequest7: {}
tt7: {}
Grant1: {}
PreGrant6: {}
RqOut7: {}
S2Out6: {}
Shift6: {}
dodrt4: {}
nPreGrant7: {}
Grant2: {}
PreGrant7: {}
S2Out7: {}
Shift7: {}
dodrt5: {}
Grant3: {}
dodrt6: {}
nPhA: {}
Grant4: {}
PhA: {}
dodrt7: {}
nPhB: {}
Grant5: {}
PhB: {}
Grant6: {}
mcmdt0: {}
nlRq0: {}
Grant7: {}
mcmdt1: {}
nReset: {}
nlRq1: {}
NoGrant: {}
lRequest0: {}
mcmdt2: {}
nlRq2: {}
lRequest1: {}
mcmdt3: {}
nlRq3: {}
NoRequest: {}
Reset: {}
lRequest2: {}
nRequest0: {}
nlRq4: {}
tt0: {}
NewRequest: {}
RqOut0: {}
lRequest3: {}
mcmdt5: {}
nPreGrant0: {}
nRequest1: {}
nlRq5: {}
tt1: {}
PreGrant0: {}
RqOut1: {}
S2Out0: {}
Shift0: {}
lRequest4: {}
mcmdt6: {}
nPreGrant1: {}
nRequest2: {}
nlRq6: {}
tt2: {}
EndNetTab
BeginTypeTab
13 --Number of CoTypes
InvertingLatch: {
shapeInfo: {shape: {(96 90) } shapeFn: {} restriction: {} }
pins: {
nQ: {physicalPins: { (68 2) south FALSE (68 88) north FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (80 2) south FALSE (90 88) north FALSE} auxInfo: {} }
D: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (94 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (94 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSPGDNmos: {
shapeInfo: {shape: {(48 90) } shapeFn: {} restriction: {} }
pins: {
t3: {physicalPins: { (16 2) south FALSE (16 88) north FALSE} auxInfo: {} }
t1: {physicalPins: { (28 2) south FALSE (28 88) north FALSE} auxInfo: {} }
t2: {physicalPins: { (40 88) north FALSE (40 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (46 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (46 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
InvertingLatchWithClear: {
shapeInfo: {shape: {(110 90) } shapeFn: {} restriction: {} }
pins: {
D: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (102 88) north FALSE (94 2) south FALSE} auxInfo: {} }
nQ: {physicalPins: { (84 88) north FALSE (82 2) south FALSE} auxInfo: {} }
Clear: {physicalPins: { (36 88) north FALSE (32 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (108 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (108 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
NOR: {
shapeInfo: {shape: {(54 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (8 2) south FALSE (8 88) north FALSE} auxInfo: {} }
in1: {physicalPins: { (36 2) south FALSE (36 88) north FALSE} auxInfo: {} }
in2: {physicalPins: { (20 88) north FALSE (20 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (52 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (52 2) south FALSE (52 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
Inverter: {
shapeInfo: {shape: {(38 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (32 2) south FALSE (32 88) north FALSE} auxInfo: {} }
in: {physicalPins: { (18 88) north FALSE (18 2) south FALSE} auxInfo: {} }
Gnd: {physicalPins: { (36 2) south FALSE (2 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (36 88) east FALSE (2 88) north FALSE} auxInfo: {} }
}
}
InvertingLatchWithPreset: {
shapeInfo: {shape: {(116 90) } shapeFn: {} restriction: {} }
pins: {
nQ: {physicalPins: { (88 88) north FALSE (88 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
Clock: {physicalPins: { (22 2) south FALSE (22 88) north FALSE} auxInfo: {} }
nPreset: {physicalPins: { (38 2) south FALSE (38 88) north FALSE} auxInfo: {} }
BiasMinus: {physicalPins: { (100 2) south FALSE (104 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (114 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (114 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSKNSPassgates: {
shapeInfo: {shape: {(136 90) } shapeFn: {} restriction: {} }
pins: {
nPhA: {physicalPins: { (74 2) south FALSE} auxInfo: {} }
Keep: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
Grant: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (134 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (134 2) south FALSE (2 2) south FALSE} auxInfo: {} }
NoRequest: {physicalPins: { (98 2) south FALSE (128 88) north FALSE} auxInfo: {} }
RqOut: {physicalPins: { (122 2) south FALSE (118 88) north FALSE} auxInfo: {} }
lRequest: {physicalPins: { (110 2) south FALSE (52 88) north FALSE} auxInfo: {} }
PhB: {physicalPins: { (52 2) south FALSE (32 88) north FALSE} auxInfo: {} }
}
}
NonInvertingLatch: {
shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (110 88) north FALSE (104 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (48 88) north FALSE (48 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (36 2) south FALSE (36 88) north FALSE} auxInfo: {} }
Q: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (118 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (118 2) south FALSE (118 2) south FALSE (118 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
StaticPrecharge: {
shapeInfo: {shape: {(52 90) } shapeFn: {} restriction: {} }
pins: {
BiasPlus: {physicalPins: { (6 88) north FALSE (6 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (32 88) north FALSE (32 2) south FALSE} auxInfo: {} }
out: {physicalPins: { (46 88) north FALSE (44 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (2 88) north FALSE (50 88) east FALSE} auxInfo: {} }
Gnd: {physicalPins: { (50 2) south FALSE (50 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
NAND: {
shapeInfo: {shape: {(56 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (50 2) south FALSE (50 88) north FALSE} auxInfo: {} }
in2: {physicalPins: { (34 2) south FALSE (34 88) north FALSE} auxInfo: {} }
in1: {physicalPins: { (18 2) south FALSE (18 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (54 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (54 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
DualRailLatch: {
shapeInfo: {shape: {(120 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (110 88) north FALSE (104 2) south FALSE} auxInfo: {} }
D: {physicalPins: { (36 88) north FALSE (36 2) south FALSE} auxInfo: {} }
Q: {physicalPins: { (8 88) north FALSE (8 2) south FALSE} auxInfo: {} }
nQ: {physicalPins: { (92 88) north FALSE (92 2) south FALSE} auxInfo: {} }
Clock: {physicalPins: { (48 88) north FALSE (48 2) south FALSE} auxInfo: {} }
Vdd: {physicalPins: { (118 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (118 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
TSBiasGen: {
shapeInfo: {shape: {(86 90) } shapeFn: {} restriction: {} }
pins: {
BiasMinus: {physicalPins: { (66 2) south FALSE (78 88) north FALSE} auxInfo: {} }
BiasPlus: {physicalPins: { (8 2) south FALSE (14 88) north FALSE} auxInfo: {} }
Vdd: {physicalPins: { (84 88) east FALSE (2 88) north FALSE} auxInfo: {} }
Gnd: {physicalPins: { (84 2) south FALSE (2 2) south FALSE} auxInfo: {} }
}
}
OAI: {
shapeInfo: {shape: {(72 90) } shapeFn: {} restriction: {} }
pins: {
out: {physicalPins: { (6 2) south FALSE (6 88) north FALSE} auxInfo: {} }
ina1: {physicalPins: { (24 88) north FALSE (24 2) south FALSE} auxInfo: {} }
ino2: {physicalPins: { (40 88) north FALSE (40 2) south FALSE} auxInfo: {} }
ino1: {physicalPins: { (56 88) north FALSE (56 2) south FALSE} auxInfo: {} }
}
}
EndTypeTab
BeginPortTab
52 --Number of Ports
BiasPlus: NIL "BiasPlus" ()
Vdd: NIL "Vdd" ()
S2Out1: NIL "S2Out1" ()
RqOut2: NIL "RqOut2" ()
Shift1: NIL "Shift1" ()
nRequest3: NIL "nRequest3" ()
BiasMinus: NIL "BiasMinus" ()
S2Out2: NIL "S2Out2" ()
RqOut3: NIL "RqOut3" ()
Shift2: NIL "Shift2" ()
nRequest4: NIL "nRequest4" ()
Gnd: NIL "Gnd" ()
S2Out3: NIL "S2Out3" ()
RqOut4: NIL "RqOut4" ()
Shift3: NIL "Shift3" ()
nRequest5: NIL "nRequest5" ()
MCmdall: NIL "MCmdall" ()
S2Out4: NIL "S2Out4" ()
RqOut5: NIL "RqOut5" ()
Shift4: NIL "Shift4" ()
nRequest6: NIL "nRequest6" ()
S2Out5: NIL "S2Out5" ()
RqOut6: NIL "RqOut6" ()
Shift5: NIL "Shift5" ()
Grant0: NIL "Grant0" ()
nRequest7: NIL "nRequest7" ()
S2Out6: NIL "S2Out6" ()
RqOut7: NIL "RqOut7" ()
Shift6: NIL "Shift6" ()
Grant1: NIL "Grant1" ()
S2Out7: NIL "S2Out7" ()
Shift7: NIL "Shift7" ()
Grant2: NIL "Grant2" ()
nPhA: NIL "nPhA" ()
Grant3: NIL "Grant3" ()
nPhB: NIL "nPhB" ()
PhA: NIL "PhA" ()
Grant4: NIL "Grant4" ()
PhB: NIL "PhB" ()
Grant5: NIL "Grant5" ()
Grant6: NIL "Grant6" ()
nReset: NIL "nReset" ()
Grant7: NIL "Grant7" ()
Reset: NIL "Reset" ()
nRequest0: NIL "nRequest0" ()
NewRequest: NIL "NewRequest" ()
RqOut0: NIL "RqOut0" ()
nRequest1: NIL "nRequest1" ()
S2Out0: NIL "S2Out0" ()
RqOut1: NIL "RqOut1" ()
Shift0: NIL "Shift0" ()
nRequest2: NIL "nRequest2" ()
EndPortTab
BeginCoTab
92 --Number of components
DDg1: (0 0) FALSE NOR 0 { out: "dodrt3" { (8 88) north FALSE (8 2) south FALSE} in2: "NewRequest" { (20 2) south FALSE (20 88) north FALSE} in1: "Keep" { (36 88) north FALSE (36 2) south FALSE}}
DDl1: (0 0) FALSE NonInvertingLatch 0 { Q: "dodrt6" { (8 2) south FALSE (8 88) north FALSE} D: "dodrt3" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
DDs1: (0 0) FALSE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "Keep" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhA" { (32 2) south FALSE (32 88) north FALSE}}
PGDA5: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out5" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq5" { (28 88) north FALSE (28 2) south FALSE}}
PGDB5: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant5" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
DDg2: (0 0) FALSE NOR 0 { out: "dodrt4" { (8 88) north FALSE (8 2) south FALSE} in2: "dodrt3" { (20 2) south FALSE (20 88) north FALSE} in1: "NoRequest" { (36 88) north FALSE (36 2) south FALSE}}
DDi2: (0 0) FALSE Inverter 0 { out: "NewRequest" { (32 88) north FALSE (32 2) south FALSE} in: "dodrt1" { (18 2) south FALSE (18 88) north FALSE}}
DDl2: (0 0) FALSE NonInvertingLatch 0 { Q: "dodrt7" { (8 2) south FALSE (8 88) north FALSE} D: "dodrt5" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
DDs2: (0 0) FALSE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "NoRequest" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhA" { (32 2) south FALSE (32 88) north FALSE}}
PGDA6: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out6" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq6" { (28 88) north FALSE (28 2) south FALSE}}
PGDB6: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant6" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
DDg3: (0 0) FALSE NOR 0 { out: "DoGrant" { (8 88) north FALSE (8 2) south FALSE} in2: "nPhA" { (20 2) south FALSE (20 88) north FALSE} in1: "dodrt6" { (36 88) north FALSE (36 2) south FALSE}}
DDi3: (0 0) FALSE Inverter 0 { out: "dodrt5" { (32 88) north FALSE (32 2) south FALSE} in: "dodrt4" { (18 2) south FALSE (18 88) north FALSE}}
DualRL0: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant0" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant0" { (8 2) south FALSE (8 88) north FALSE} D: "tt0" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
PGDA7: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out7" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq7" { (28 88) north FALSE (28 2) south FALSE}}
PGDB7: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant7" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
DDg4: (0 0) FALSE NOR 0 { out: "DoShift" { (8 88) north FALSE (8 2) south FALSE} in2: "nPhA" { (20 2) south FALSE (20 88) north FALSE} in1: "dodrt7" { (36 88) north FALSE (36 2) south FALSE}}
DualRL1: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant1" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant1" { (8 2) south FALSE (8 88) north FALSE} D: "tt1" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
DualRL2: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant2" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant2" { (8 2) south FALSE (8 88) north FALSE} D: "tt2" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
GDTl1: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant0" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant0" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreA1: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant1" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant1" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB1: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift2" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant1" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
DualRL3: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant3" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant3" { (8 2) south FALSE (8 88) north FALSE} D: "tt3" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
GDTl2: (0 0) FALSE InvertingLatchWithClear 0 { nQ: "Shift1" { (82 2) south FALSE (84 88) north FALSE} D: "nPreGrant0" { (8 2) south FALSE (8 88) north FALSE} Clear: "Reset" { (32 2) south FALSE (36 88) north FALSE} Clock: "DoShift" { (20 2) south FALSE (20 88) north FALSE}}
INVA0: (0 0) FALSE Inverter 0 { out: "lRequest0" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq0" { (18 2) south FALSE (18 88) north FALSE}}
INVB0: (0 0) FALSE Inverter 0 { out: "tt0" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out0" { (18 2) south FALSE (18 88) north FALSE}}
VLPreA2: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant2" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant2" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB2: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift3" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant2" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
DualRL4: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant4" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant4" { (8 2) south FALSE (8 88) north FALSE} D: "tt4" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
INVA1: (0 0) FALSE Inverter 0 { out: "lRequest1" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq1" { (18 2) south FALSE (18 88) north FALSE}}
INVB1: (0 0) FALSE Inverter 0 { out: "tt1" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out1" { (18 2) south FALSE (18 88) north FALSE}}
KNS0: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut0" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant0" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest0" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
VLPreA3: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant3" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant3" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB3: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift4" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant3" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
DualRL5: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant5" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant5" { (8 2) south FALSE (8 88) north FALSE} D: "tt5" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
INVA2: (0 0) FALSE Inverter 0 { out: "lRequest2" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq2" { (18 2) south FALSE (18 88) north FALSE}}
INVB2: (0 0) FALSE Inverter 0 { out: "tt2" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out2" { (18 2) south FALSE (18 88) north FALSE}}
KNS1: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut1" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant1" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest1" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
VLPreA4: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant4" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant4" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB4: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift5" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant4" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
DualRL6: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant6" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant6" { (8 2) south FALSE (8 88) north FALSE} D: "tt6" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
INVA3: (0 0) FALSE Inverter 0 { out: "lRequest3" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq3" { (18 2) south FALSE (18 88) north FALSE}}
INVB3: (0 0) FALSE Inverter 0 { out: "tt3" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out3" { (18 2) south FALSE (18 88) north FALSE}}
KNS2: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut2" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant2" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest2" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
VLPreA5: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant5" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant5" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB5: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift6" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant5" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
DualRL7: (0 0) FALSE DualRailLatch 0 { nQ: "PreGrant7" { (92 2) south FALSE (92 88) north FALSE} Q: "nPreGrant7" { (8 2) south FALSE (8 88) north FALSE} D: "tt7" { (36 2) south FALSE (36 88) north FALSE} Clock: "PhB" { (48 2) south FALSE (48 88) north FALSE}}
INVA4: (0 0) FALSE Inverter 0 { out: "lRequest4" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq4" { (18 2) south FALSE (18 88) north FALSE}}
INVB4: (0 0) FALSE Inverter 0 { out: "tt4" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out4" { (18 2) south FALSE (18 88) north FALSE}}
KNS3: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut3" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant3" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest3" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
NVL0: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq0" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest0" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
VLPreA15: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant7" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant7" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreA6: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Grant6" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant6" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoGrant" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB15: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift0" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant7" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
VLPreB6: (0 0) FALSE InvertingLatchWithPreset 0 { nQ: "Shift7" { (88 2) south FALSE (88 88) north FALSE} D: "nPreGrant6" { (6 88) north FALSE (6 2) south FALSE} nPreset: "nReset" { (38 88) north FALSE (38 2) south FALSE} Clock: "DoShift" { (22 88) north FALSE (22 2) south FALSE}}
INVA5: (0 0) FALSE Inverter 0 { out: "lRequest5" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq5" { (18 2) south FALSE (18 88) north FALSE}}
INVB5: (0 0) FALSE Inverter 0 { out: "tt5" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out5" { (18 2) south FALSE (18 88) north FALSE}}
KNS4: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut4" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant4" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest4" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
MCDg1: (0 0) FALSE NAND 0 { out: "mcmdt2" { (50 88) north FALSE (50 2) south FALSE} in2: "PhB" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt1" { (18 88) north FALSE (18 2) south FALSE}}
MCDi1: (0 0) FALSE Inverter 0 { out: "mcmdt9" { (32 88) north FALSE (32 2) south FALSE} in: "NoGrant" { (18 2) south FALSE (18 88) north FALSE}}
MCDl1: (0 0) FALSE InvertingLatch 0 { nQ: "mcmdt1" { (68 88) north FALSE (68 2) south FALSE} D: "mcmdt9" { (8 2) south FALSE (8 88) north FALSE} Clock: "PhA" { (20 2) south FALSE (20 88) north FALSE}}
MCDs1: (0 0) FALSE StaticPrecharge 0 { BiasPlus: "BiasPlus" { (6 2) south FALSE (6 88) north FALSE} Gnd: "Gnd" { (2 2) south FALSE (50 2) south FALSE (50 2) south FALSE} Vdd: "Vdd" { (50 88) east FALSE (2 88) north FALSE} out: "NoGrant" { (44 2) south FALSE (46 88) north FALSE} Clock: "nPhB" { (32 2) south FALSE (32 88) north FALSE}}
NVL1: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq1" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest1" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
INVA6: (0 0) FALSE Inverter 0 { out: "lRequest6" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq6" { (18 2) south FALSE (18 88) north FALSE}}
INVB6: (0 0) FALSE Inverter 0 { out: "tt6" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out6" { (18 2) south FALSE (18 88) north FALSE}}
KNS5: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut5" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant5" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest5" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
MCDg2: (0 0) FALSE NAND 0 { out: "MCmdall" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt3" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt2" { (18 88) north FALSE (18 2) south FALSE}}
MCDi2: (0 0) FALSE Inverter 0 { out: "mcmdt7" { (32 88) north FALSE (32 2) south FALSE} in: "PhA" { (18 2) south FALSE (18 88) north FALSE}}
NVL2: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq2" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest2" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
INVA7: (0 0) FALSE Inverter 0 { out: "lRequest7" { (32 88) north FALSE (32 2) south FALSE} in: "nlRq7" { (18 2) south FALSE (18 88) north FALSE}}
INVB7: (0 0) FALSE Inverter 0 { out: "tt7" { (32 88) north FALSE (32 2) south FALSE} in: "S2Out7" { (18 2) south FALSE (18 88) north FALSE}}
KNS6: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut6" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant6" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest6" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
MCDg3: (0 0) FALSE OAI 0 { out: "mcmdt3" { (6 88) north FALSE (6 2) south FALSE} ina1: "MCmdall" { (24 2) south FALSE (24 88) north FALSE} ino2: "mcmdt5" { (40 2) south FALSE (40 88) north FALSE} ino1: "PhA" { (56 2) south FALSE (56 88) north FALSE}}
NVL3: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq3" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest3" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
PGDA0: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out0" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq0" { (28 88) north FALSE (28 2) south FALSE}}
PGDB0: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant0" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
KNS7: (0 0) FALSE TSKNSPassgates 0 { RqOut: "RqOut7" { (118 88) north FALSE (122 2) south FALSE} NoRequest: "NoRequest" { (128 88) north FALSE (98 2) south FALSE} Keep: "Keep" { (18 88) north FALSE (18 2) south FALSE} Grant: "Grant7" { (6 2) south FALSE (6 88) north FALSE} lRequest: "lRequest7" { (52 88) north FALSE (110 2) south FALSE} PhB: "PhB" { (32 88) north FALSE (52 2) south FALSE} nPhA: "nPhA" { (74 2) south FALSE}}
MCDg4: (0 0) FALSE NAND 0 { out: "mcmdt5" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt6" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt2" { (18 88) north FALSE (18 2) south FALSE}}
NVL4: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq4" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest4" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
PGDA1: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out1" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq1" { (28 88) north FALSE (28 2) south FALSE}}
PGDB1: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant1" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
MCDg5: (0 0) FALSE NAND 0 { out: "mcmdt6" { (50 88) north FALSE (50 2) south FALSE} in2: "mcmdt7" { (34 88) north FALSE (34 2) south FALSE} in1: "mcmdt5" { (18 88) north FALSE (18 2) south FALSE}}
NVL5: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq5" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest5" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
PGDA2: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out2" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq2" { (28 88) north FALSE (28 2) south FALSE}}
PGDB2: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant2" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
bg1: (0 0) FALSE TSBiasGen 0 { BiasPlus: "BiasPlus" { (14 88) north FALSE (8 2) south FALSE} BiasMinus: "BiasMinus" { (78 88) north FALSE (66 2) south FALSE} Gnd: "Gnd" { (2 2) south FALSE (84 2) south FALSE} Vdd: "Vdd" { (2 88) north FALSE (84 88) east FALSE}}
NVL6: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq6" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest6" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
PGDA3: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out3" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq3" { (28 88) north FALSE (28 2) south FALSE}}
PGDB3: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant3" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
NVL7: (0 0) FALSE NonInvertingLatch 0 { Q: "nlRq7" { (8 2) south FALSE (8 88) north FALSE} D: "nRequest7" { (36 88) north FALSE (36 2) south FALSE} Clock: "PhA" { (48 2) south FALSE (48 88) north FALSE}}
PGDA4: (0 0) FALSE TSPGDNmos 0 { t2: "S2Out4" { (40 2) south FALSE (40 88) north FALSE} t3: "PhB" { (16 88) north FALSE (16 2) south FALSE} t1: "nlRq4" { (28 88) north FALSE (28 2) south FALSE}}
PGDB4: (0 0) FALSE TSPGDNmos 0 { t2: "NoGrant" { (40 2) south FALSE (40 88) north FALSE} t3: "PreGrant4" { (16 88) north FALSE (16 2) south FALSE} t1: "PhA" { (28 88) north FALSE (28 2) south FALSE}}
EndCoTab
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