/*                                                           */
/* Copyright (C) 1987 by Bryan Preas and Ken Roberts.        */
/*                All rights reserved.                       */
/*                                                           */
/* Modified March 24, 1987: added bindings to pads           */
/*                                                           */
/* Format Test: Smoke.yal                                    */
/*                                                           */
/*                                                           */
/*  Module name = INV                                        */
/*  Width = 20 microns, Height = 160 microns                 */
/*                                                           */
MODULE inv;
 TYPE STANDARD;
 WIDTH 20;
 HEIGHT 160;
/*                                                           */
/*  Define the external connections: I1 and O1               */
/*                                                           */
 IOLIST;
/* <signalname><terminaltype><side> <position><width><layer> */
   I          I             TOP    5.0       3.0    METAL2;
   I          I             BOTTOM 5.0       3.0    METAL2;
   X          O             TOP    15.0      3.0    METAL2;
   X          O             BOTTOM 15.0      3.0    METAL2;
 ENDIOLIST;
 ENDMODULE;
/*                                                           */
/*  Module name = Feedthru                                     */
/*  Width = 10 microns, Height = 160 microns                 */
/*                                                           */
MODULE Feedthru;
 TYPE FEEDTHROUGH;
 WIDTH 10;
 HEIGHT 160;
/*                                                           */
/*  Define the external connection: F1                       */
/*                                                           */
 IOLIST;
/* <signalname> <terminaltype><side><position><width><layer> */
   FeedIn           F             TOP    5.0      3.0    METAL2;
   FeedIn           F             BOTTOM 5.0      3.0    METAL2;
 ENDIOLIST;
 ENDMODULE;
/*                                                           */
/*  Module name = vdd                                     */
/*  Width = 10 microns, Height = 160 microns                 */
/*                                                           */
MODULE Vdd;
 TYPE STANDARD;
 WIDTH 10;
 HEIGHT 160;
/*                                                           */
/*  Define the external connection: Vdd                       */
/*                                                           */
 IOLIST;
/* <signalname> <terminaltype><side><position><width><layer> */
   vdd           F             TOP    5.0      3.0    METAL2;
   vdd           F             BOTTOM 5.0      3.0    METAL2;
 ENDIOLIST;
 ENDMODULE;
 
/*                                                           */
/*  Module name = Gnd                                     */
/*  Width = 10 microns, Height = 160 microns                 */
/*                                                           */
MODULE Gnd;
 TYPE STANDARD;
 WIDTH 10;
 HEIGHT 160;
/*                                                           */
/*  Define the external connection: gnd                       */
/*                                                           */
 IOLIST;
/* <signalname> <terminaltype><side><position><width><layer> */
   gnd           F             TOP    5.0      3.0    METAL2;
   gnd           F             BOTTOM 5.0      3.0    METAL2;
 ENDIOLIST;
 ENDMODULE;

/*                                                           */
/*  Module name = nand2                                       */
/*  Width = 30 microns, Height = 160 microns                 */
/*                                                           */
 MODULE nand2;
 TYPE STANDARD;
 WIDTH 30; HEIGHT 160;
/*                                                           */
/*  Define the external connections: I1, I2 and OUT          */
/*                                                           */
 IOLIST;
/* <signalname><terminaltype><side> <position><width><layer> */
   I-A          I             TOP    5.0       3.0    METAL2;
   I-A          I             BOTTOM 5.0       3.0    METAL2;
   I-B          I             TOP    15.0      3.0    METAL2;
   I-B          I             BOTTOM 15.0      3.0    METAL2;
   X         O             TOP    25.0      3.0    METAL2;
   X         O             BOTTOM 25.0      3.0    METAL2;
 ENDIOLIST;
 ENDMODULE;
/*                                                           */
/*  Module name = INPUTPAD                                   */
/*  Width = 200 microns, Height = 200 microns                */
/*                                                           */
MODULE INPUTPAD;
 TYPE PAD;
 WIDTH 200; HEIGHT 200;
/*                                                           */
/*  Define the external connections: OUT and INPAD           */
/*                                                           */
 IOLIST;
/* <signalname><terminaltype><side> <position><width><layer> */
   OUT         O             BOTTOM 100.0     3.0    METAL2;
   INPAD       PI            TOP    100.0     50.0   METAL2;
 ENDIOLIST;
 ENDMODULE;
/*                                                           */
/*  Module name = OUTPUTPAD                                  */
/*  Width = 200 microns, Height = 200 microns                */
/*                                                           */
MODULE OUTPUTPAD;
 TYPE PAD;
 WIDTH 200; HEIGHT 200;
/*                                                           */
/*  Define the external connections: IN and OUTPAD           */
/*                                                           */

IOLIST;

/* <signalname><terminaltype><side> <position><width><layer> */
   IN          I             BOTTOM 100.0     3.0    METAL2;
   OUTPAD      PO            TOP    100.0     50.0   METAL2;
 ENDIOLIST;
 ENDMODULE;
/*                                                           */ 
/*  Module to be laid out: name = AND                        */
/*                                                           */
MODULE AND;
 TYPE PARENT;
/*                                                           */
/*  Define the external connections: I1, I2 and OUT          */
/*  Pad positions are not fixed                              */
/*                                                           */
 IOLIST;
/* <signalname> <terminaltype><side><position><width><layer> */
  I1           PI;
  I2           PI;
  OUT          PO;
 ENDIOLIST;
/*                                                           */
/*  Define the instances of primitive modules and the        */
/*    connectivity                                           */
/*                                                           */
 NETWORK;
/* <instancename> <modulename> <signalname> <signalname>     */
   I1             INPUTPAD     IN1            I1;
   I2             INPUTPAD     IN2            I2;
   OUT            OUTPUTPAD    OUTPUT           OUT;
   INV            inv          NOUT          OUTPUT;
   NAND           nand2         IN1            IN2          NOUT;
 ENDNETWORK;
 ENDMODULE;