
    <<CreateCoreForSmokeImpl.mesa>>
        <<Copyright Ó 1988 by Xerox Corporation.  All rights reserved.>>
        <<Bryan Preas May 4, 1988 3:33:03 pm PDT>>

    DIRECTORY
        CD, Core, CoreClasses, CoreDirectory, PWCore, RTTestUtil;
    CreateCoreForSmokeImpl: CEDAR PROGRAM
        IMPORTS CoreDirectory, PWCore, RTTestUtil
        EXPORTS RTTestUtil = BEGIN
        OPEN Core, CoreClasses, CoreDirectory, PWCore, RTTestUtil;


    CreateCoreForinv: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["I", "X", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        invCellType: CellType _ CreateRecordCell["inv", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "inv", invCellType, TRUE];
        SetGet[invCellType, libDesign];
        RETURN [invCellType];
        END;

    CreateCoreForFeedthru: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["FeedIn", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        FeedthruCellType: CellType _ CreateRecordCell["Feedthru", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "Feedthru", FeedthruCellType, TRUE];
        SetGet[FeedthruCellType, libDesign];
        RETURN [FeedthruCellType];
        END;

    CreateCoreForVdd: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["vdd", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        VddCellType: CellType _ CreateRecordCell["Vdd", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "Vdd", VddCellType, TRUE];
        SetGet[VddCellType, libDesign];
        RETURN [VddCellType];
        END;

    CreateCoreForGnd: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["gnd", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        GndCellType: CellType _ CreateRecordCell["Gnd", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "Gnd", GndCellType, TRUE];
        SetGet[GndCellType, libDesign];
        RETURN [GndCellType];
        END;

    CreateCoreFornand2: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["I-A", "I-B", "X", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        nand2CellType: CellType _ CreateRecordCell["nand2", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "nand2", nand2CellType, TRUE];
        SetGet[nand2CellType, libDesign];
        RETURN [nand2CellType];
        END;

    CreateCoreForINPUTPAD: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["OUT", "INPAD", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        INPUTPADCellType: CellType _ CreateRecordCell["INPUTPAD", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "INPUTPAD", INPUTPADCellType, TRUE];
        SetGet[INPUTPADCellType, libDesign];
        RETURN [INPUTPADCellType];
        END;

    CreateCoreForOUTPUTPAD: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        pubWires: Wire _ CreateWire[LIST["IN", "OUTPAD", "Vdd", "Gnd"]];
        privateWires: Wire _ NIL;
        internWires: Wire _ UnionWire[pubWires, privateWires];
        OUTPUTPADCellType: CellType _ CreateRecordCell["OUTPUTPAD", pubWires, internWires, NIL];
        [] _ Insert[coreLibrary, "OUTPUTPAD", OUTPUTPADCellType, TRUE];
        SetGet[OUTPUTPADCellType, libDesign];
        RETURN [OUTPUTPADCellType];
        END;

    CreateCoreForAND: PUBLIC PROC [libDesign: CD.Design, coreLibrary: Library] RETURNS [CellType] = BEGIN
        <<Create a Core CellType>>

        gnd: CellType _ CreateCoreForGnd[libDesign, coreLibrary];
        vdd: CellType _ CreateCoreForVdd[libDesign, coreLibrary];
        pubWires: Wire _ CreateWire[LIST["IN1", "IN2", "OUTPUT", "Vdd", "Gnd"]];
        privateWires: Wire _ CreateWire[LIST["NOUT"]];
        internWires: Wire _ UnionWire[pubWires, privateWires];
        nand2CellType: CellType _ CreateCoreFornand2[libDesign, coreLibrary];
        NAND: CellInstance _ CreateInstance[LIST["IN1", "IN2", "NOUT", "Vdd", "Gnd"], nand2CellType, "NAND", internWires];
        invCellType: CellType _ CreateCoreForinv[libDesign, coreLibrary];
        INV: CellInstance _ CreateInstance[LIST["NOUT", "OUTPUT", "Vdd", "Gnd"], invCellType, "INV", internWires];
        ANDCellType: CellType _ CreateRecordCell["AND", pubWires, internWires, LIST[INV, NAND]];
        [] _ Insert[coreLibrary, "AND", ANDCellType, TRUE];
        SetGet[ANDCellType, libDesign];
        RETURN [ANDCellType];
        END;


        END.