CreateCoreForSmokeImpl.mesa
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Bryan Preas May 4, 1988 3:33:03 pm PDT
DIRECTORY
CD, Core, CoreClasses, CoreDirectory, PWCore, RTTestUtil;
CreateCoreForSmokeImpl:
CEDAR
PROGRAM
IMPORTS CoreDirectory, PWCore, RTTestUtil
EXPORTS RTTestUtil = BEGIN
OPEN Core, CoreClasses, CoreDirectory, PWCore, RTTestUtil;
CreateCoreForinv:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["I", "X", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
invCellType: CellType ← CreateRecordCell["inv", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "inv", invCellType, TRUE];
SetGet[invCellType, libDesign];
RETURN [invCellType];
END;
CreateCoreForFeedthru:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["FeedIn", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
FeedthruCellType: CellType ← CreateRecordCell["Feedthru", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "Feedthru", FeedthruCellType, TRUE];
SetGet[FeedthruCellType, libDesign];
RETURN [FeedthruCellType];
END;
CreateCoreForVdd:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["vdd", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
VddCellType: CellType ← CreateRecordCell["Vdd", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "Vdd", VddCellType, TRUE];
SetGet[VddCellType, libDesign];
RETURN [VddCellType];
END;
CreateCoreForGnd:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["gnd", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
GndCellType: CellType ← CreateRecordCell["Gnd", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "Gnd", GndCellType, TRUE];
SetGet[GndCellType, libDesign];
RETURN [GndCellType];
END;
CreateCoreFornand2:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["I-A", "I-B", "X", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
nand2CellType: CellType ← CreateRecordCell["nand2", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "nand2", nand2CellType, TRUE];
SetGet[nand2CellType, libDesign];
RETURN [nand2CellType];
END;
CreateCoreForINPUTPAD:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["OUT", "INPAD", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
INPUTPADCellType: CellType ← CreateRecordCell["INPUTPAD", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "INPUTPAD", INPUTPADCellType, TRUE];
SetGet[INPUTPADCellType, libDesign];
RETURN [INPUTPADCellType];
END;
CreateCoreForOUTPUTPAD:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
pubWires: Wire ← CreateWire[LIST["IN", "OUTPAD", "Vdd", "Gnd"]];
privateWires: Wire ← NIL;
internWires: Wire ← UnionWire[pubWires, privateWires];
OUTPUTPADCellType: CellType ← CreateRecordCell["OUTPUTPAD", pubWires, internWires, NIL];
[] ← Insert[coreLibrary, "OUTPUTPAD", OUTPUTPADCellType, TRUE];
SetGet[OUTPUTPADCellType, libDesign];
RETURN [OUTPUTPADCellType];
END;
CreateCoreForAND:
PUBLIC
PROC [libDesign:
CD.Design, coreLibrary: Library]
RETURNS [CellType] =
BEGIN
Create a Core CellType
gnd: CellType ← CreateCoreForGnd[libDesign, coreLibrary];
vdd: CellType ← CreateCoreForVdd[libDesign, coreLibrary];
pubWires: Wire ← CreateWire[LIST["IN1", "IN2", "OUTPUT", "Vdd", "Gnd"]];
privateWires: Wire ← CreateWire[LIST["NOUT"]];
internWires: Wire ← UnionWire[pubWires, privateWires];
nand2CellType: CellType ← CreateCoreFornand2[libDesign, coreLibrary];
NAND: CellInstance ← CreateInstance[LIST["IN1", "IN2", "NOUT", "Vdd", "Gnd"], nand2CellType, "NAND", internWires];
invCellType: CellType ← CreateCoreForinv[libDesign, coreLibrary];
INV: CellInstance ← CreateInstance[LIST["NOUT", "OUTPUT", "Vdd", "Gnd"], invCellType, "INV", internWires];
ANDCellType: CellType ← CreateRecordCell["AND", pubWires, internWires, LIST[INV, NAND]];
[] ← Insert[coreLibrary, "AND", ANDCellType, TRUE];
SetGet[ANDCellType, libDesign];
RETURN [ANDCellType];
END;