DIRECTORY CMosB, DesignRules; GCHybridRulesImpl: CEDAR PROGRAM IMPORTS CMosB, DesignRules = BEGIN OPEN DesignRules; Generate: PROC = { rules: Rules _ NewRules[$Hybrid, CMosB.cmosB, 1, 1]; pDif: Layer _ NewLayer[rules, $PDif, "CPD", "P+ well diffusion", "Defines P+ diffused areas when diffusion does not contact substrate or well", CMosB.pdif]; nDif: Layer _ NewLayer[rules, $NDif, "CND", "N+ diffusion", "Defines N+ diffused areas when diffusion does not contact substrate or well", CMosB.ndif]; poly: Layer _ NewLayer[rules, $Poly, "CP", "Polysilicon", "Defines poly gates and poly interconnect", CMosB.pol]; contact: Layer _ NewLayer[rules, $Contact, "CC", "Contact", "Defines contact openings to diffusion and poly", CMosB.cut]; metal1: Layer _ NewLayer[rules, $Metal1, "CM", "Metal 1", "Defines first metal interconnects", CMosB.met]; via: Layer _ NewLayer[rules, $Via, "CC2", "Via", "Defines openings in the insulator between first and second metal", CMosB.cut2]; metal2: Layer _ NewLayer[rules, $Metal2, "CC2", "Metal 2", "Defines second metal interconnects", CMosB.met2]; pad: Layer _ NewLayer[rules, $Pad, "CG", "Pad Window 1", "Defines openings on the passivation layer for probing and bonding", CMosB.ovg]; NewRule[rules, $NDifWidth, width, nDif, NIL, 2, "n dif width"]; NewRule[rules, $PDifWidth, width, pDif, NIL, 2, "p dif width"]; NewRule[rules, $NDifSpace, intraspace, nDif, NIL, 35, "n dif space", 10]; NewRule[rules, $PDifSpace, intraspace, pDif, NIL, 35, "p dif space", 10]; NewRule[rules, $PolyWidth, width, poly, NIL, 2, "poly width"]; NewRule[rules, $PolySpace, intraspace, poly, NIL, 25, "poly space", 10]; NewRule[rules, $PolyNDifSpace, interspace, poly, nDif, 1, "poly ndif space"]; NewRule[rules, $PolyPDifSpace, interspace, poly, pDif, 1, "poly pdif space"]; NewRule[rules, $ContactWidth, width, contact, NIL, 2, "contact width"]; NewRule[rules, $ContactMaxWidth, maxWidth, contact, NIL, 5, "contact max width"]; NewRule[rules, $ContactSpace, intraspace, contact, NIL, 3, "contact space"]; NewRule[rules, $PolyContactSurround, surround, poly, contact, 1, "poly contact surround"]; NewRule[rules, $PDifContactSurround, surround, pDif, contact, 1, "p dif contact surround"]; NewRule[rules, $NDifContactSurround, surround, nDif, contact, 1, "n dif contact surround"]; NewRule[rules, $Metal1ContactSurround, surround, metal1, contact, 1, "metal 1 contact surround"]; NewRule[rules, $Metal1Width, width, metal1, NIL, 25, "metal 1 width"]; NewRule[rules, $Metal1Space, intraspace, metal1, NIL, 25, "metal 1 space"]; NewRule[rules, $ViaWidth, width, via, NIL, 2, "via width"]; NewRule[rules, $ViaMaxWidth, maxWidth, via, NIL, 5, "via max width"]; NewRule[rules, $ViaSpace, intraspace, via, NIL, 4, "vias pace"]; NewRule[rules, $Metal1ViaSurround, surround, metal1, via, 1, "metal 1 via surround"]; NewRule[rules, $Metal2ViaSurround, surround, metal2, via, 1, "metal 2 via surround"]; NewRule[rules, $PolyViaSpace, interspace, poly, via, 2, "poly via space"]; NewRule[rules, $PolyViaSurround, surround, poly, via, 3, "poly via surround"]; NewRule[rules, $DifCutViaSpace, special, via, contact, 2, "dif cut via space"]; NewRule[rules, $PolyCutViaSpace, interspace, via, contact, 3, "poly cut via space"]; NewRule[rules, $Metal2Width, width, metal2, NIL, 25, "metal 2 width"]; NewRule[rules, $Metal2Space, intraspace, metal2, NIL, 25, "metal 2 space"]; NewMicronRule[rules, $PadMetalWidth, special, NIL, NIL, 25, "pad metal width"]; NewMicronRule[rules, $PadMetalViaSurround, special, NIL, NIL, 5, "pad metal via surround", 10]; NewMicronRule[rules, $Metal2PadSurround, surround, metal2, pad, 5, "metal 2 pad surround"]; NewMicronRule[rules, $PadMetalSpace, special, NIL, NIL, 25, "pad metal space"]; { metal1Surround: RuleValue _ FindRuleValue[rules, $Metal1ContactSurround]; NewHoleType[rules, $PolyContact, metal1, poly, contact, metal1Surround, FindRuleValue[rules, $PolyContactSurround]]; NewHoleType[rules, $NDifContact, metal1, nDif, contact, metal1Surround, FindRuleValue[rules, $NDifContactSurround]]; NewHoleType[rules, $PDifContact, metal1, pDif, contact, metal1Surround, FindRuleValue[rules, $PDifContactSurround]]; }; NewHoleType[rules, $Via, metal1, metal2, via, FindRuleValue[rules, $Met1ViaSurround], FindRuleValue[rules, $Met2ViaSurround]]; DesignRules.RegisterRuleSet[rules]; }; Generate[]; END. GCHybridRulesImpl.mesa Copyright Ó 1988 by Xerox Corporation. All rights reserved. Preas, April 8, 1988 4:06:20 pm PDT This file defines the Hybrid design rules. This rendition does not contain all of rules, nor are all rules complete. Should you require program access to a number from the Hybrid rules, DO NOT place it in your own code. Contact the maintainer of this file and it will be added. Drawn Layers Generalized Layout Rules Diffusion Rules Min Width Min space between N+ to N+, P+ to P+, or P+ to N+ when the two adjacent diffusions are located on the same substrate and one or both are intended to be isolated from the substrate (such as a drain diffusion). Polysilicon Rules Min width Min poly spacing Min poly spacing to unrelated diffusion $PolyNDifSpace used by ECAD Checking this rule by rectangle pairs requires that the errors between the gate poly and the channel diffusion be suppressed when a transistor is exploded. Contact Rules Contact to P+ And N+ Diffusion And Poly: Min contact size Max contact size Must know that the contact rectangle is not part of a butting contact. Min contact to contact spacing Min poly overlap of contact Must know that contact rectangle belongs to poly contact. Min diffusion overlap of contact Must know what sort of diffusion contact the contact rectangle belongs to. Min metal 1 overlap of contact to poly and diffusion Metal 1 Rules Min width Min space Max current carrying capability 0.5 mA/m Via Rules Min size Max size Except at the pads. Min via to via space Min metal 1 and 2 overlap of via Min via to poly spacing We might want to change this so that via over poly is always illegal. Min poly overlap of via (when via is inside of the poly) Min via to contact of diffusion spacing Min via to contact to poly spacing This rule and 6.7.8 together define the spacing between via and contact. If this rule becomes smaller than 6.7.8 then 6.7.8 becomes interspace and this rule becomes special. Max current carrying capability is 0.07 mA per micron of via hole periphery Metal 2 Rules Min width Min space Max current carrying capability 1.0 mA/m Additional Layout Requirements (not shrinkable) Most of the dimensions specified here are in microns. When they are drawn on the layout grid the number of Lambda must be chosen in such a way that the final dimensions in microns are not smaller than the ones indicated (i.e. bond pad dimensions in microns are not shrinkable). Bonding pads consist of a metal 1 pad, a via opening over metal 1, a metal 2 pad and opening into the passivation layers. Minimum pad dimension for metal 1 & 2 Min metal 1 & 2 overlap of via Min metal 2 overlap of pad mask (layer 70) opening Min spacing between metal edges of adjacent pads This is set to 51 instead of 50.8 so that the scaling is integer. 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