Create a Core design

BEGIN

coreLibrary: CoreDirectory.Library ← CoreDirectory.CreateLibrary[];

libDesign: CD.Design ← CDIO.ReadDesign[libName, NIL, CDIO.GetWorkingDirectory[]];

nandWires: Core.Wire ← RTTestUtil.CreateWire[LIST["I-A", "I-B", "X", "Vdd", "Gnd"]];

nand: Core.CellType ← RTTestUtil.CreateRecordCell["nand2.mask", nandWires, nandWires, NIL];

invWires: Core.Wire ← RTTestUtil.CreateWire[LIST["I", "X", "Vdd", "Gnd"]];

inverter: Core.CellType ← RTTestUtil.CreateRecordCell["invBuffer.mask", invWires, invWires, NIL];

pubWires: Core.Wire ← RTTestUtil.CreateWire[LIST["InA", "InB", "Out", "Vdd", "Gnd"]];

privateWires: Core.Wire ← RTTestUtil.CreateWire[LIST["NOut"]];

internWires: Core.Wire ← RTTestUtil.UnionWire[pubWires, privateWires];

nandInst: CoreClasses.CellInstance ← RTTestUtil.CreateInstance[LIST["InA", "InB", "NOut", "Vdd", "Gnd"], nand, "nandInst", internWires];

invInst: CoreClasses.CellInstance ← RTTestUtil.CreateInstance[LIST["NOut", "Out", "Vdd", "Gnd"], inverter, "invInst", internWires];

GCTest: Core.CellType ← RTTestUtil.CreateRecordCell["GCTest", pubWires, internWires, LIST[nandInst, invInst]];

CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "InA"], GC.sideProp, GC.bottomSideValue];

CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "InB"], GC.sideProp, GC.topSideValue];

CoreProperties.PutWireProp[CoreOps.FindWire[internWires, "Out"], GC.sideProp, GC.leftSideValue];

[] ← CoreDirectory.RegisterLibrary[coreLibrary, libName];

[] ← CoreDirectory.Insert[coreLibrary, "nand2.mask", nand, TRUE];

[] ← CoreDirectory.Insert[coreLibrary, "invBuffer.mask", inverter, TRUE];

CoreProperties.PutCellTypeProp[on: nand, prop: $SCPlacableElement, value: $SCPlacableElement];

CoreProperties.PutCellTypeProp[on: inverter, prop: $SCPlacableElement, value: $SCPlacableElement];

PWCore.SetGet[nand, libDesign];

PWCore.SetGet[inverter, libDesign];

RETURN [GCTest];

END;