DIRECTORY CD, CDIO, CDSymbolicObjects, Core, CoreClasses, CoreFlat, CoreGeometry, CoreOps, CoreProperties, GC, PWCore, PWPins, Rope, RTCoreUtil, RTStructure, Sinix, Sisyph;GCPWCore: CEDAR PROGRAMIMPORTS CDIO, CDSymbolicObjects, CoreGeometry, CoreOps, CoreProperties, GC, PWCore, PWPins, RTCoreUtil, Sisyph= BEGINGCLayoutAtom: ATOM _ PWCore.RegisterLayoutAtom[$GC, GCLayout, GCDecorate, GCAttibutes];GCLayout: PWCore.LayoutProc = {result: GC.Result;context: GC.Context;name: Rope.ROPE _ CoreOps.GetCellTypeName[cellType];hMaterial: Rope.ROPE _ "metal";vMaterial: Rope.ROPE _ "metal2";rules: GC.DesignRules _ GC.CreateDesignRules[technologyKey, hMaterial, vMaterial];structure: RTStructure.Structure _ GC.CreateStructure[cellType, RTCoreUtil.defaultFlatten, PinFilter, rules, extractMode.decoration];GC.InitialPlace[structure, CDIO.MakeName[name, "init", CDIO.GetWorkingDirectory[]]];context _ GC.CreateContext["GCTest", structure, rules];GC.DoInitialGlobalRoute[context];result _ GC.DoDetailRoute[context];RETURN[result.object]};GCDecorate: PUBLIC PWCore.DecorateProc = {EachPublicPin: PWPins.InstanceEnumerator = {name: Rope.ROPE _ CDSymbolicObjects.GetName[inst];wire: Core.Wire _ CoreOps.FindWire[cellType.public, name];pins: LIST OF CoreGeometry.Instance;IF wire=NIL THEN RETURN;pins _ CoreGeometry.GetPins[extractMode.decoration, wire];CoreGeometry.PutPins[extractMode.decoration, wire, CONS [[inst.ob, inst.trans], pins]];};CoreOps.VisitRootAtomics[cellType.public, SmashPins];-- CoreGeometry.PutIR[extractMode.decoration, cellType, CD.InterestRect[obj]];[] _ PWPins.EnumerateEdgePins[obj, EachPublicPin];};GCAttibutes: PWCore.AttributesProc = {-- [cellType: Core.CellType]FindSideForEachPin: CoreGeometry.EachWirePinProc = {PushPropOnAtomic: PROC [wire: Core.Wire] ~ {CoreProperties.PutWireProp[wire, GC.sideProp, ref];};ref: REF _ SELECT side FROMbottom => GC.bottomSideValue,top => GC.topSideValue,right => GC.rightSideValue,left => GC.leftSideValue,ENDCASE => GC.noSideValue;IF wire.size=0 THEN CoreProperties.PutWireProp[wire, GC.sideProp, ref] ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic];};decoration: CoreGeometry.Decoration _ Sisyph.mode.decoration;DOIF CoreGeometry.HasObject[decoration, cellType] THEN {[] _ CoreGeometry.EnumerateWireSides[decoration, cellType, FindSideForEachPin];EXIT};IF cellType.class.recast = NIL THEN EXIT;cellType _ CoreOps.Recast[cellType]ENDLOOP;}; technologyKey: ATOM _ $cmosB;		-- $cmosA or $cmosBlibName: Rope.ROPE _ "CMOSB";extractMode: Sinix.Mode _ PWCore.extractMode;SmashPins: PROC [wire: Core.Wire] = {CoreGeometry.PutPins[extractMode.decoration, wire, NIL]};PinFilter: RTStructure.CorePinFilterProc ~ {rules: GC.DesignRules _ NARROW[userData];SELECT side FROMbottom, top => keepIt _  rules.horizRules.branchLayer = layer;left, right => keepIt _  rules.vertRules.branchLayer = layer;ENDCASE => keepIt _ FALSE;};END.    Ø  GCPWCore.mesaCopyright c 1986 by Xerox Corporation.  All rights reserved.Preas, July 11, 1986 10:15:48 am PDT-- The cellType to layout is a record cellType containing elements to be routed; the layout proc flattens the Core description and calls the general cell router.IPMainViewer.BuildViewer["GCTest"];IPMainViewer.SetTopTo[NARROW[context.topology], structure.name, FALSE];-- Puts on public wires a property indicating their side[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL _ FALSE]PROC [wire: Core.Wire, instance: CD.Instance, range: Range, side: RTBasic.Side, layer: CD.Layer, userData: REF ANY] RETURNS [keepIt: BOOLEAN _ TRUE];Êz  –"cedar" style˜ codešœ™Kšœ
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