DIRECTORY CD, Core, CoreFlat, CoreGeometry, D2Basic, RProperties, Rope, Route, RTBasic, RTCoreUtil, RTStructure; GC: CEDAR DEFINITIONS = BEGIN RopeList: TYPE = LIST OF Rope.ROPE; Layer: TYPE = CD.Layer; Rect: TYPE = D2Basic.Rect; RefRect: TYPE = REF Rect; Pos: TYPE = D2Basic.Vector; Number: TYPE = D2Basic.Number; SideOrNone: TYPE = RTBasic.SideOrNone; Side: TYPE = RTBasic.Side; DirectionOrNone: TYPE = RTBasic.DirectionOrNone; Direction: TYPE = RTBasic.Direction; PropList: TYPE = RProperties.PropList; Error: ERROR [errorType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; Signal: SIGNAL [signalType: ErrorType _ callingError, explanation: Rope.ROPE _ NIL]; ErrorType: TYPE = {programmingError, callingError, noResource, designRuleViolation, other}; DesignRules: TYPE = REF DesignRulesRec; DesignRulesRec: TYPE = RECORD[ horizLayer, vertLayer: Rope.ROPE, horizRules, vertRules: Route.DesignRules, technology: CD.Technology, properties: PropList _ NIL]; metalHorizontalRules, metalVerticalRules: DesignRules; -- default design rules using $CmosB CreateDesignRules: PROC [technologyKey: ATOM, horizLayer, vertLayer: Rope.ROPE, properties: PropList _ NIL] RETURNS [designRules: DesignRules]; sideProp, bottomSideValue, rightSideValue, topSideValue, leftSideValue, noSideValue: ATOM; interestingProperties: RTCoreUtil.PropertyKeys; Parms: TYPE = REF ParmsRec; ParmsRec: TYPE = RECORD [ opt: Route.Optimization _ full, -- controls runtime vs quality signalIncomplete: BOOLEAN _ TRUE, -- SIGNAL if there are any incompletes signalSinglePinNets: BOOLEAN _ TRUE -- SIGNAL if there are any single pin nets ]; defaultParms: Parms; Context: TYPE = REF ContextRec; ContextRec: TYPE = RECORD [ name: Rope.ROPE _ NIL, -- name or the cell being constructed rules: DesignRules _ NIL, -- widths and spacings to be used structure: RTStructure.Structure _ NIL, -- structure specifications parms: Parms _ NIL, topology: REF ANY _ NIL, -- for internal use only topologicalOrder: REF ANY _ NIL, -- for internal use only properties: PropList _ NIL]; Result: TYPE = REF ResultRec; ResultRec: TYPE = RECORD[ context: Context, object: CD.Object, polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: INT _ 0, numIncompletes: INT _ 0, incompleteNets: RopeList _ NIL]; CreateStructure: PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc _ NIL, pinFilter: RTStructure.CorePinFilterProc _ NIL, userData: REF ANY _ NIL, decoration: CoreGeometry.Decoration, defaultLib: CD.Design _ NIL] RETURNS [structure: RTStructure.Structure]; CreateContext: PROC [name: Rope.ROPE _ NIL, structure: RTStructure.Structure, designRules: DesignRules _ metalHorizontalRules, parms: Parms _ defaultParms, properties: PropList _ NIL] RETURNS [context: Context]; InitialPlace: PROC [structure: RTStructure.Structure, initFile: Rope.ROPE]; DoInitialGlobalRoute: PROC [context: Context]; DoImproveGlobalRoute: PROC [context: Context]; DoDetailRoute: PROC [context: Context] RETURNS [result: Result]; Destroy: PROC [context: Context]; END.  GC.mesa Copyright c 1985, 1986 by Xerox Corporation. All rights reserved. Last Edited by: Preas, August 21, 1986 5:28:22 pm PDT Theory This interface defines the public data structures and operations to define a general cell object from a structure description. Common Types Errors Design Rules Define the general cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2". Properties Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire Used to specify all the properties that aer interesting to GC General Cell Context and Result The general cell router will signal if design rule violations are found in the input. Proceeding from the signals may cause design rule violations in the routing!! Setting the Signal Booleans to FALSE should be used with caution!! Derive the interconnection requirements from a Core Data structure. Create a General Cell context. The General Cell context definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition. See Structure for utilities to create a structure temporary initial placement: read from a file General Cell Optimization and Construction The following operations are available for a standard cell design. Determine strategic paths for the wiring. Determine strategic paths for the wiring. Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object. 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