GCPWCore.mesa
Copyright © 1986 by Xerox Corporation. All rights reserved.
Preas, July 11, 1986 10:15:48 am PDT
DIRECTORY CD, CDIO, CDSymbolicObjects, Core, CoreClasses, CoreFlat, CoreGeometry, CoreOps, CoreProperties, GC, PWCore, PWPins, Rope, RTCoreUtil, RTStructure, Sinix, Sisyph;
GCPWCore:
CEDAR
PROGRAM
IMPORTS CDIO, CDSymbolicObjects, CoreGeometry, CoreOps, CoreProperties, GC, PWCore, PWPins, RTCoreUtil, Sisyph
= BEGIN
GCLayoutAtom:
ATOM ← PWCore.RegisterLayoutAtom[$GC, GCLayout, GCDecorate, GCAttibutes];
-- The cellType to layout is a record cellType containing elements to be routed; the layout proc flattens the Core description and calls the general cell router.
GCLayout: PWCore.LayoutProc = {
result: GC.Result;
context: GC.Context;
name: Rope.ROPE ← CoreOps.GetCellTypeName[cellType];
hMaterial: Rope.ROPE ← "metal";
vMaterial: Rope.ROPE ← "metal2";
rules: GC.DesignRules ← GC.CreateDesignRules[technologyKey, hMaterial, vMaterial];
structure: RTStructure.Structure ← GC.CreateStructure[cellType, RTCoreUtil.defaultFlatten, PinFilter, rules, extractMode.decoration];
GC.InitialPlace[structure, CDIO.MakeName[name, "init", CDIO.GetWorkingDirectory[]]];
context ← GC.CreateContext["GCTest", structure, rules];
GC.DoInitialGlobalRoute[context];
IPMainViewer.BuildViewer["GCTest"];
IPMainViewer.SetTopTo[NARROW[context.topology], structure.name, FALSE];
result ← GC.DoDetailRoute[context];
RETURN[result.object]};
GCDecorate:
PUBLIC PWCore.DecorateProc = {
EachPublicPin: PWPins.InstanceEnumerator = {
name: Rope.ROPE ← CDSymbolicObjects.GetName[inst];
wire: Core.Wire ← CoreOps.FindWire[cellType.public, name];
pins: LIST OF CoreGeometry.Instance;
IF wire=NIL THEN RETURN;
pins ← CoreGeometry.GetPins[extractMode.decoration, wire];
CoreGeometry.PutPins[extractMode.decoration, wire, CONS [[inst.ob, inst.trans], pins]];
};
CoreOps.VisitRootAtomics[cellType.public, SmashPins];
-- CoreGeometry.PutIR[extractMode.decoration, cellType, CD.InterestRect[obj]];
[] ← PWPins.EnumerateEdgePins[obj, EachPublicPin];
};
-- Puts on public wires a property indicating their side
GCAttibutes: PWCore.AttributesProc = {
-- [cellType: Core.CellType]
FindSideForEachPin: CoreGeometry.EachWirePinProc = {
[wire: Core.Wire, instance: CD.Instance, min: INT, max: INT, side: CoreGeometry.Side, layer: CD.Layer] RETURNS [quit: BOOL ← FALSE]
PushPropOnAtomic:
PROC [wire: Core.Wire] ~ {
CoreProperties.PutWireProp[wire, GC.sideProp, ref];
};
ref:
REF ←
SELECT side
FROM
bottom => GC.bottomSideValue,
top => GC.topSideValue,
right => GC.rightSideValue,
left => GC.leftSideValue,
ENDCASE => GC.noSideValue;
IF wire.size=0 THEN CoreProperties.PutWireProp[wire, GC.sideProp, ref]
ELSE CoreOps.VisitRootAtomics[wire, PushPropOnAtomic];
};
decoration: CoreGeometry.Decoration ← Sisyph.mode.decoration;
DO
IF CoreGeometry.HasObject[decoration, cellType]
THEN {
[] ← CoreGeometry.EnumerateWireSides[decoration, cellType, FindSideForEachPin];
EXIT};
IF cellType.class.recast = NIL THEN EXIT;
cellType ← CoreOps.Recast[cellType]
ENDLOOP;
};
technologyKey: ATOM ← $cmosB; -- $cmosA or $cmosB
libName: Rope.ROPE ← "CMOSB";
extractMode: Sinix.Mode ← PWCore.extractMode;
SmashPins:
PROC [wire: Core.Wire] = {CoreGeometry.PutPins[extractMode.decoration, wire,
NIL]};
PinFilter: RTStructure.CorePinFilterProc ~ {
PROC [wire: Core.Wire, instance: CD.Instance, range: Range, side: RTBasic.Side, layer: CD.Layer, userData: REF ANY] RETURNS [keepIt: BOOLEAN ← TRUE];
rules: GC.DesignRules ← NARROW[userData];
SELECT side
FROM
bottom, top => keepIt ← rules.horizRules.branchLayer = layer;
left, right => keepIt ← rules.vertRules.branchLayer = layer;
ENDCASE => keepIt ← FALSE;
};
END.