DIRECTORY
CD, Core, CoreFlat, CoreGeometry, D2Basic, RProperties, Rope, Route, RTBasic, RTCoreUtil, RTStructure;
Common Types
RopeList: TYPE = LIST OF Rope.ROPE;
Layer: TYPE = CD.Layer;
Rect: TYPE = D2Basic.Rect;
RefRect: TYPE = REF Rect;
Pos: TYPE = D2Basic.Vector;
Number: TYPE = D2Basic.Number;
SideOrNone: TYPE = RTBasic.SideOrNone;
Side: TYPE = RTBasic.Side;
DirectionOrNone: TYPE = RTBasic.DirectionOrNone;
Direction: TYPE = RTBasic.Direction;
PropList: TYPE = RProperties.PropList;
Errors
Error: ERROR [errorType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
Signal: SIGNAL [signalType: ErrorType ← callingError, explanation: Rope.ROPE ← NIL];
ErrorType: TYPE = {programmingError, callingError, noResource, designRuleViolation, other};
Design Rules
DesignRules: TYPE = REF DesignRulesRec;
DesignRulesRec:
TYPE =
RECORD[
horizLayer, vertLayer: Rope.ROPE,
horizRules, vertRules: Route.DesignRules,
technology: CD.Technology,
properties: PropList ← NIL];
metalHorizontalRules, metalVerticalRules: DesignRules;
-- default design rules using $CmosB
CreateDesignRules:
PROC [technologyKey:
ATOM, horizLayer, vertLayer: Rope.
ROPE, properties: PropList ←
NIL]
RETURNS [designRules: DesignRules];
Define the general cell design rules. technologyKey values must correspond to one of the ChipNDale technologies. horizLayer, vertLayer should be "poly", "metal" or "metal2".
Properties
sideProp, bottomSideValue, rightSideValue, topSideValue, leftSideValue, noSideValue:
ATOM;
Used to specify the side on which a public pin is to be placed. sideProp with (mumble)Value should be a property/value on a public wire
interestingProperties: RTCoreUtil.PropertyKeys;
Used to specify all the properties that aer interesting to GC
General Cell Context and Result
Parms: TYPE = REF ParmsRec;
ParmsRec:
TYPE =
RECORD [
opt: Route.Optimization ← full, -- controls runtime vs quality
signalIncomplete: BOOLEAN ← TRUE, -- SIGNAL if there are any incompletes
signalSinglePinNets: BOOLEAN ← TRUE -- SIGNAL if there are any single pin nets
];
The general cell router will signal if design rule violations are found in the input. Proceeding from the signals may cause design rule violations in the routing!! Setting the Signal Booleans to FALSE should be used with caution!!
Context: TYPE = REF ContextRec;
ContextRec:
TYPE =
RECORD [
name: Rope.ROPE ← NIL, -- name or the cell being constructed
rules: DesignRules ← NIL, -- widths and spacings to be used
structure: RTStructure.Structure ← NIL, -- structure specifications
parms: Parms ← NIL,
topology: REF ANY ← NIL, -- for internal use only
topologicalOrder: REF ANY ← NIL, -- for internal use only
properties: PropList ← NIL];
Result: TYPE = REF ResultRec;
ResultRec:
TYPE =
RECORD[
context: Context,
object: CD.Object,
polyLength, metalLength, metal2Length, polyToMetal, metalToMetal2: INT ← 0,
numIncompletes: INT ← 0,
incompleteNets: RopeList ← NIL];
CreateStructure:
PROC [cellType: Core.CellType, flattenCellType: RTCoreUtil.FlattenCellTypeProc ← NIL, pinFilter: RTStructure.CorePinFilterProc ←
NIL, userData:
REF
ANY ←
NIL, decoration: CoreGeometry.Decoration, defaultLib: CD.Design ← NIL]
RETURNS [structure: RTStructure.Structure];
Derive the interconnection requirements from a Core Data structure.
CreateContext:
PROC [name: Rope.
ROPE ←
NIL, structure: RTStructure.Structure, designRules: DesignRules ← metalHorizontalRules, parms: Parms ← defaultParms, properties: PropList ←
NIL]
RETURNS [context: Context];
Create a General Cell context. The General Cell context definition includes the design rules (conductor and via widths and spacings) for the routing channels as well as the circuit structure definition. See Structure for utilities to create a structure
InitialPlace:
PROC [structure: RTStructure.Structure, initFile: Rope.
ROPE];
temporary initial placement: read from a file
General Cell Optimization and Construction
The following operations are available for a standard cell design.
DoInitialGlobalRoute:
PROC [context: Context];
Determine strategic paths for the wiring.
DoImproveGlobalRoute:
PROC [context: Context];
Determine strategic paths for the wiring.
DoDetailRoute:
PROC [context: Context]
RETURNS [result: Result];
Determine actual wiring paths. Create a ChipNDale object and include the placement and routing in the object.