Pad Frame Layout and Routing for VLSI Circuits
Bryan Preas
Xerox Palo Alto Research Center
3333 Coyote Hill Road, Palo Alto, CA 94304
phone: (415) 494-4845, fax: (415) 494-5810
1 Introduction
Pad frame layout and routing addresses the problem of connecting the logic, or inner cell, of an integrated circuit through bonding pads to the environment. Three interrelated problems must be addressed together to solve this problem successfully:
Pad frame layout generates the ring of bonding pads with the correct aspect and size and in the proper position. Power busses may be included within the pad frame.
Power distribution includes the means to supply power to the bonding pads as well as to supply the inner cell. Reliability and electrical principles combine to impose constraints on power wiring topology.
Pad ring routing connects pins (both signal and power) on the inner cell to pins on the bonding pads.
This paper presents a new solution to pad frame layout and routing. The solution combines standard functions to produce a general solution. This work builds on layout framework research at the Xerox Palo Alto Research Center [Barth-a].
Previously, pad frame layout has not been considered a separate topic. Typically, pad frame layout is performed in a preprogrammed fashion; the only options available to the circuit designer are those provided by the programmer. It is difficult for this options and parameters approach to meet the needs of modern VLSI circuits. The approach described here brings all the power of modern module generators to bear.
Research into power distribution has focused on determining wiring topologies that allow power distribution on a single layer (i.e., without vias). [Zahir] provides the condition for the existence of planar routing for two nets (a cut set exists for the pins of the two nets on all of the cells). Most power routing algorithms assume this condition. For example, see [Rothermel, Xiong]. Recently Zahir's planarity condition has been bypassed by allowing multiple power pads and a forest of power supply nets [Haruyama] or loops [Dai].
However, large, high performance circuits dictate even more complex power supply topologies. We have found the most (area) efficient topology is a grid. Grid distribution topologies also tend to even the peaks in current distribution but require two layers of interconnection. Thus, we must account for the extra resistance in wires caused by vias and must take precautions to insure highly reliable vias. Analysis of grid distribution topologies is difficult, but given the approximate nature of electromigration models and the difficulty in determining peak power supply currents (especially in large CMOS circuits), high accuracy is unnecessary.
Previous pad ring routing algorithms fall into two categories:
A single routing channel with concentric tracks and radial columns [Smith], or
Four trapezoidal channels (one on each side of the inner cell) [McGehee].
Both categories have drawbacks which reduce routing efficiency and preclude use of active cells. Furthermore, they require a routing model different from standard channel and switchbox routers. Thus, systems that use these algorithms cannot make use of highly developed channel and switchbox routers. This contrasts with our approach; the detailed routers are the same as those used throughout the design system.
The remainder of this paper describes the new pad ring layout and routing approach. Section 2 describes the problem being solved while Section 3 provides an overview of the approach and discusses the division of the layout surface into routing areas. Section 4 describes the algorithms in detail while Section 5 presents results for two typical circuits.
2 Problem Description
Pad layout and routing connects an inner cell to its external environment through bonding pads.
The physical layout of the inner cell and the bonding pads may be completed (the exact geometry is available) or the cells may be active [Preas]. (They can sense their environment and adjust their layout to suit.) An example of the utility of active cells is the ability to size the power busses according to the power supply current that must be fed through the cell. This means the layout must first be done topologically. Then the cells are sized, and finally, the geometric layout is performed.
The connectivity between the inner cell and the pad frame is specified by a structural description [Barth-b] while the connectivity within the cells is provided by the encompassing layout system. The connectivity within the cells is necessary since arbitrary layout synthesis tools may leave some nets disconnected and expect the pad frame router (the router of last resort) to connect any remaining disconnected wires. In particular, power and ground nets are often partially disconnected.
Typical input to the layout and routing program is a schematic such as Figure 1. Figures 2 shows the layout produced for this schematic.
3 Layout Approach
The pad frame is constructed directly from the schematic description using module generators. The remainder of the layout surface is routing area and is divided as shown in Figure 3. The routing area closest to the inner cell is used for both signal and power nets, and routing is performed by channel and switchbox routers. The next outermost ring is devoted to busses that supply power to the inner cell and is constructed by module generators. Signal wiring that connects to the bonding pad on a side must cross the power bus modules. The outermost annular ring (typically 0 to 3 tracks thick) is routed by four channel router invocations (one for each side). This area is used to route to bonding pad pins within the shadow of power supply pins on the inner cell. Bonding pad pins that are not within a shadow are routed straight across these outer channels. If wiring is not required in any routing area, its size is automatically reduced to zero.
4 Layout and Routing Algorithms
4.1 Overview
The top level algorithm is shown in Figure 4. These steps are described in the remainder of this section.
 global route the signals (Steiner approximations and shortest path algorithms)
 size cells (if active cells are used)
 construct pad frame from schematics definition (module generator)
 construct power bus modules (module generator)
 route the four outer channels (channel router)
 route the signal routing areas (channel and switchbox routers)
Figure 4 The top level algorithm for pad frame layout and routing is shown.
4.2 Global Routing
Global routing finds an assignment of wiring segments to signal routing areas (channels or switchboxes) that minimizes the area subject to constraints of connectivity and electrical characteristics (primarily wire widths). Wire widths are determined by properties of the nets or properties of the pins on the inner cell. The global router knows which pins are connected within the cells and exploits this information to improve the global routing. Power supply nets may be routed with the other signals (with wider wires, of course) as in Figure 5, or these nets may be connected directly across the signal channels to power busses as in Figure 2.
4.3 Pad Frame Construction
Pad frames are constructed based on the schematic. This schematic definition can be as simple as a row of abutted bonding pad cells as shown in Figure 5. However, all of the power of modern module generators [Barth-a] is available. Double rows of bonding pads and dedicated power busses are easily accommodated as in Figure 2.
4.4 Power Busses for Inner the Cell
These routing areas are constructed by module generators. The normal configuration is a double ring of metal where one ring carries Gnd and the other carries Vdd. One layer of metal supplies the inner cell power pins, and the other metal layer connects to the appropriate power pads. Signal wiring that connects to pads are included in the power bus module as close to the respective bonding pad pin as possible.
4.5 Detailed Routing
An advantage of this approach is that only channel and switchbox routers are needed for detailed routing. These routers are well understood and produce very good routing [Deutsch]. Extensions are provided to guarantee completion in the presence of constraint loops and to allow pins at any location and wires of any width.
5 Results
The pad frame layout and routing package has been in use at Xerox PARC for two years and has been used in a wide range of designs. Two radically different layouts are shown in Figures 2 and 5. Figure 5 shows a general cell layout in which the power nets are routed with the signal nets. Figure 2 shows a standard cell layout in which all the routing areas defined in Figure 3 are present.
References
[Barth—a] Barth, R., L., Monier, and B. Serlet, "Patchwork: layout from schematic annotations," Proc. of 25th Design Automation Conference, pp 250-255, June 12-15, 1988.
[Barth—b] Barth, R., and B. Serlet, "A structural representation for VSLI designs," Proc. of 25th Design Automation Conference, pp 237-242, June 12-15, 1988.
[Dai] Dai, W-M., H. Chen, R. Dutta, M. Jackson, E. Kuh, M. Marek-Sadowski, M. Sato, D. Wong, and X—M. Xiong, "BEAR: a new building-block layout system," Proc. of International Conference on Computer-Aided Design-87, pp. 34-37, November 9-12, 1987.
[Deutsch] Deutsch, D. N., "A 'dogleg' channel router," Proc. of 13th Design Automation Conference, pp. 425-433, June, 1976.
[Haruyama] Haruyama, S., and D. Fussel "A new area-efficient power routing algorithm for VLSI layout," Proc. of International Conference on Computer-Aided Design-87, pp. 38-41, November 9-12, 1987.
[McGehee] McGehee, R. K., "A practical moat router," Proc. of 24th Design Automation Conference, pp. 216-221, June 28-July 1, 1987.
[Preas] Preas, B. T., "An approach to placement for rectilinear cells," presented at Physical Design Workshop: Placement and Floorplanning, Hilton Head, South Carolina, April 1987.
[Rothermel] Rothermel, H. J., and D. A. Mlynski, "Computation of power supply nets in VLSI layout," Proc. of 18th Design Automation Conference, pp. 53-63, 1981.
[Smith] Smith, L. R. et al., "A new area router, the LRS algorithm," Proc. of ICCC '82, pp. 256-259, Sept.-Oct. 1982.
[Xiong] Xiong, X—M., and E. S. Kuh "The scan line approach to power and ground wiring," Proc. of International Conference on Computer-Aided Design-86, pp. 6-9, November 11-13, 1986.
[Zahir] Zahir, A. S., and A. El Gamal, "Single layer routing of power and ground networks in integrated circuits," Journal of Digital Systems, volume VI, number 1, pp. 56-63, Spring 1982.
Figure 1 A schematic is the source description that drives the pad frame layout and routing process. This schematic produced the layout shown in Figure 2.
Figure 2 This layout example corresponds to the schematic shown in Figure 1. All of the routing areas defined in Figure 3 are utilized.
Figure 3 The layout surface is divided into these routing areas. After global routing (which looks at the big picture), each of the routing areas is implemented by a local operation.
Figure 5 In this layout example, the power nets are routed with the signal nets. Thus, no separate power bus modules or outer routing channels are needed.
filed on
///Users/preas.pa/papers/Cabbage.tioga
/Indigo/Autolayout/Documentation/Cabbage.tioga
October 1, 1988 4:19:01 pm PDT