IPChipRose:
CEDAR
DEFINITIONS
IMPORTS IPParams = BEGIN OPEN RC: ReadConnection;
Ref: TYPE = REF Rep;
Rep:
TYPE =
RECORD[
cellTypeName: Rope.ROPE,
nets,
ports,
instances,
types: SymTab.Ref
];
--(1) Entry for a port in ports
PortRec:
TYPE =
RECORD[
eqClass,
net: Rope.ROPE,
direction: RC.Direction --{Unknown, Input, Output, InputOutput}
];
--(2) Entry for a net in nets
NetRec: TYPE = RECORD[generation: RC.Generation];
--(3) Entry for an instance in instances
InstanceRec:
TYPE =
RECORD[
type: Rope.ROPE,
pinNets: LIST OF PinNetRec,
origin: REF IP.IntVector ← NIL, --Set by initFile. origin # NIL (ie. instance has been intially placed) => active = TRUE
orient: IP.Orientation -- set by initFile
];
PinNetRec: TYPE = RECORD[pin, net: Rope.ROPE];
--(4) Entry for a type in types
TypeRec:
TYPE =
RECORD[
origin: IP.IntVector, --keep this so that relative pin positions can be computed
instances: LIST OF Rope.ROPE, --All instances of this type
pins: LIST OF REF IP.PinRep, --name, physicalPins, auxInfo
shape: REF ShapeRep ← NIL, --width, height and the sizes of the four corners
shapeFn: REF ← NIL, --Function for shape determintaion
restriction: REF ← NIL -- Restriction on shape (and orientation)
];
ShapeRep: TYPE = IP.ShapeRep;
--The following 4 enumeration functions provide easy access to
-- information in IPChipRose.Ref. Changing contents of val is permanent.
EachNetAction: TYPE = PROC[net: Rope.ROPE, val: REF NetRec] RETURNS [quit: BOOL ← FALSE];
EachPortAction: TYPE = PROC[port: Rope.ROPE, val: REF PortRec] RETURNS [quit: BOOL ← FALSE];
EachTypeAction: TYPE = PROC[type: Rope.ROPE, val: REF TypeRec] RETURNS [quit: BOOL ← FALSE];
EachInstanceAction: TYPE = PROC[instance: Rope.ROPE, val: REF InstanceRec] RETURNS [quit: BOOL ← FALSE];
Which: TYPE = {net, port, type, instance};
CreateFrom:
PROC[roseFile, chipFile, typFile, initFile: Rope.
ROPE ←
NIL, chipBeforeTyp:
BOOL ←
FALSE, debug:
BOOL ← IPParams.DebugSystem]
RETURNS [Ref];
-- NB: roseFile = Rosemary structure file; chipFile = File from chipNdale;
-- typFile = Alternative to chipFile; initFile = initialization file;
-- chipFile or typFile can be NIL as long as all types are definitions are available
-- initFile is the initialization file for the placer
-- if ~ debug then extract only those types used by instances in roseFile
-- if chipBeforeTyp then chipFile has higher precedence than typFile
Fetch:
PROC[r: Ref, name: Rope.
ROPE, what: Which]
RETURNS [
REF];
-- Have to NARROW results yourself.
Nets: PROC[r: Ref, action: EachNetAction];
Ports: PROC[r: Ref, action: EachPortAction];
Types: PROC [r: Ref, action: EachTypeAction];
Instances: PROC[r: Ref, action: EachInstanceAction];
END.