-- MemoryController.df
-- Copyright (C) 1986 by Xerox Corporation.  All rights reserved.
-- Last Edited by: Gasbarro November 28, 1988 9:44:13 am PST
-- contains layout and simulation for the Dragon memory controller chip 

Exports [Dragon]<Dragon7.0>Top>
  MemoryController.df                          28-Nov-88 14:15:31 PST

Exports [Dragon]<Dragon7.0>MemoryController>
  +DRam.bcd!2                                   06-May-88 11:55:10 PDT
  +DRamImpl.bcd!12                              17-Oct-88 18:59:31 PDT
  +TestMC.bcd!44                                21-Oct-88 12:22:10 PDT
  +WIGenerator.bcd!4                            06-Oct-87 14:38:17 PDT
  +RAMControlFSM.bcd!4                          01-Apr-88 12:17:59 PST
  +ResponseChecker.bcd!3                        24-Nov-87 09:18:55 PST
  +ResponseCheckerImpl.bcd!13                   01-Apr-88 12:17:57 PST
  +MCWireIcons.bcd!13                           01-Apr-88 12:17:41 PST
  +MCEccImpl.bcd!5                              01-Apr-88 12:17:45 PST
  +MCUtils.bcd!1                                23-Nov-87 15:13:11 PST
  +MCUtilsImpl.bcd!2                            24-Nov-87 10:53:28 PST

  MemoryController.dale!41                     20-Oct-88 08:17:05 PDT
  MCLogo.dale!3                                18-Nov-87 08:38:43 PST
  MemoryController.install!4                   12-Oct-88 10:40:11 PDT
  MC.cm!12                                     19-Oct-87 08:20:25 PDT
  MCSimulate.cm!4                              19-Oct-88 18:16:11 PDT
  MCMTSReplay.cm!2                             19-Oct-88 18:03:31 PDT
  MCLayout.cm!7                                05-Nov-87 12:23:30 PST
  MCLayoutA.cm!8                               01-Dec-87 17:26:37 PST
  MCLayoutB.cm!9                               02-Dec-87 09:51:37 PST
  MCMint.cm!7                                  04-Nov-87 15:49:59 PST
  MCTransistorSimulate.cm!2                    04-Nov-87 12:30:15 PST
  MCLichen.cm!4                                11-Nov-87 12:24:00 PST
  MCConnectivityCheck.cm!2                     06-Nov-87 15:16:48 PST

Directory [Dragon]<Dragon7.0>MemoryController>
  DRam.mesa!2                                  06-May-88 11:55:03 PDT
  DRamImpl.mesa!3                              17-Oct-88 18:58:23 PDT
  MCUtils.mesa!1                               23-Nov-87 15:13:08 PST
  MCUtilsImpl.mesa!2                           24-Nov-87 10:53:25 PST
  TestMC.mesa!31                               21-Oct-88 12:21:41 PDT
  +TestECC.bcd!15                               01-Apr-88 12:17:49 PST
  TestECC.mesa!1                               24-Apr-87 08:07:57 PDT
  +CommandDecodeFSM.bcd!5                       01-Apr-88 12:18:00 PST
  CommandDecodeFSM.mesa!1                      15-Apr-87 09:56:31 PDT
  +RequestControlFSM.bcd!4                      01-Apr-88 12:18:17 PST
  RequestControlFSM.mesa!2                     01-Jul-87 15:57:19 PDT
  +ReplyControlFSM.bcd!5                        01-Apr-88 12:17:54 PST
  ReplyControlFSM.mesa!3                       26-Jun-87 13:04:14 PDT
  +RequestArbiterFSM.bcd!3                      01-Apr-88 12:18:09 PST
  RequestArbiterFSM.mesa!1                     10-Apr-87 14:37:20 PDT
  RAMControlFSM.mesa!2                         12-Oct-87 08:35:55 PDT
  ResponseCheckerImpl.mesa!2                   09-Oct-87 10:54:32 PDT
  ResponseChecker.mesa!2                       09-Oct-87 08:02:04 PDT
  MCWireIcons.mesa!8                           06-Oct-87 07:45:25 PDT
  MCEccImpl.mesa!3                             29-Jun-87 21:46:09 PDT
  WIGenerator.mesa!1                           07-May-87 16:34:57 PDT

  PalToTTT.mesa!1                              14-Jul-87 18:11:26 PDT
  MCRequestControl.mesa!1                      14-Jul-87 09:28:20 PDT

  MemoryControllerLayout.dale!1                01-Dec-87 01:42:11 PST
  MemoryControllerEmptyICPack.dale!1           11-Oct-88 15:39:44 PDT
  MemoryControllerIcPack.pinsBottom!1          12-Apr-88 13:21:38 PDT
  MemoryControllerIcPack.pinsLeft!1            12-Apr-88 13:21:36 PDT
  MemoryControllerIcPack.pinsRight!1           12-Apr-88 13:21:37 PDT
  MemoryControllerIcPack.pinsTop!1             12-Apr-88 13:21:38 PDT
  MemoryController.mtspackage!1                11-Oct-88 17:32:47 PDT
  MCSpice.dale!1                               05-Nov-87 11:16:57 PST
  MC.dale!1                                    08-Jun-87 15:26:45 PDT
  DPRam.dale!1                                 09-Dec-86 12:28:49 PST
  MemoryControllerDataSheetDoc.tioga!8         09-Feb-88 10:15:44 PST
  MCDataSheetFigs.dale!7                       12-Feb-88 13:59:41 PST
  MemoryControllerSlides.tioga!4               02-Aug-88 16:23:15 PDT
  MemoryControllerSpec.tioga!1                 24-Sep-86 16:47:36 PDT

-- new MC (verilog version)
  MemoryController2.dale!1                     14-Oct-88 14:23:00 PDT
  DynabusPadsSC.dale!1                         11-Oct-88 08:39:11 PDT
  MCDataPathSC.dale!1                          10-Oct-88 16:35:00 PDT


Exports Imports [Dragon]<Dragon7.0>Top>MCDataPath.df Of ~=
Exports Imports [Dragon]<Dragon7.0>Top>DBus.df Of ~=
Exports Imports [Dragon]<Dragon7.0>Top>Arbiter25.df Of ~=
Exports Imports [CedarChest7.0]<Top>Graphs0.df Of ~=

Imports [Dragon]<Dragon7.0>Top>DynaBus.df Of ~=
  Using [DynaBusInterface.bcd, +DynaBusInterfaceImpl.bcd]

Imports [Dragon]<Dragon7.0>Top>MCDataPath.df Of ~=
  Using [MCDataPath.bcd]

Imports [DATools7.0]<Top>Boole.df Of ~=
  Using [Boole.bcd, BooleCore.bcd, FiniteStateAutomata.bcd]

Imports [DATools7.0]<Top>Core.df Of ~=
  Using [BitOps.bcd, Core.bcd, CoreClasses.bcd, CoreCreate.bcd, CoreFlat.bcd, CoreOps.bcd, CoreProperties.bcd]

Imports [DATools7.0]<Top>CDCommon25.df Of ~=
  Using [CD.bcd, CDCells.bcd, CDCommandOps.bcd, CDIO.bcd, CDOps.bcd, CDProperties.bcd, CDSequencer.bcd, CDViewer.bcd, D2Basic.bcd]

Imports [DATools7.0]<Top>D2Basic3.df Of ~=
  Using [D2Orient.bcd]

Imports [DATools7.0]<Top>Extract.df Of ~=
  Using [CoreCDUser.bcd, Sisyph.bcd, WireIcons.bcd]

Imports [DATools7.0]<Top>MTSVector.df Of ~=
  Using [MTSVector.bcd, PGA400.mtsFixture]

Imports [DATools7.0]<Top>Rosemary.df Of ~=
  Using [Rosemary.bcd, RosemaryUser.bcd, RosemaryVector.bcd, Ports.bcd]

Imports [CedarChest7.0]<Top>Graphs0.df Of ~=
  Using [FIFOQueue.bcd]

Imports [CedarChest7.0]<Top>TerminalIO.df Of ~=
  Using [TerminalIO.bcd]

Imports [Cedar7.0]<Top>BootPackages.df Of ~=
  Using [CardTab.bcd, Random.bcd]

Imports [Cedar7.0]<Top>IO.df Of ~=
  Using [IO.bcd]

Imports [Cedar7.0]<Top>MesaRuntime.df Of ~=
  Using [Basics.bcd]

Imports [Cedar7.0]<Top>Rope.df Of ~=
  Using [Rope.bcd]

Imports [Cedar7.0]<Top>SafeStorage.df Of ~=
  Using [Atom.bcd]