DIRECTORY TRDataPath, Core, CoreClasses, CoreOps, CoreProperties, CMosB, DataPath, IO, Ports, Rope, Rosemary, RosemaryUser;

TRDataPathImpl: CEDAR PROGRAM
IMPORTS CoreClasses, CoreOps, CoreProperties, DataPath, IO, Ports, Rosemary, RosemaryUser
EXPORTS TRDataPath =

BEGIN
BusShort:	PUBLIC PROC[size: INT] RETURNS[wire: Core.Wire] = {
sub: Core.Wire _ CoreOps.CreateWires[0, "sw"];
wire _ CoreOps.CreateWires[size, "w"];
FOR i: INT IN [0..size) DO wire[i] _ sub ENDLOOP};

Trans: PUBLIC PROC[type: CoreClasses.TransistorType, length, width: INT]
RETURNS [cellType: Core.CellType] = {
name: IO.ROPE _ IO.PutFR["%g%gx%g",
IO.rope[CoreClasses.transistorTypeNames[type]],
IO.int[length],
IO.int[width]];
cellType _ CoreClasses.CreateTransistor[type, length, width, name]
};
DPEdgeFFName: Rope.ROPE = Rosemary.Register[roseClassName: "DPEdgeFFSeq", init: DPEdgeFFSeqInit, evalSimple: DPEdgeFFSeqSimple, scheduleIfClockEval: TRUE];

DPEdgeFFTopName: Rope.ROPE = Rosemary.Register[roseClassName: "DPEdgeFFTopSeq", init: DPEdgeFFSeqInit, evalSimple: DPEdgeFFSeqSimple, scheduleIfClockEval: TRUE];

DPEdgeFFSeqState: TYPE = REF DPEdgeFFSeqStateRec;
DPEdgeFFSeqStateRec: TYPE = RECORD [
in, out, ck: Ports.Port _ NIL,
master, slave: Ports.LevelSequence];

DPEdgeFFSeqInit: Rosemary.InitProc = {
state: DPEdgeFFSeqState;
IF oldStateAny=NIL THEN {
size: NAT _ p[Ports.PortIndex[cellType.public, "D"]].ls.size;
state _ NEW[DPEdgeFFSeqStateRec];
state.master _ NEW[Ports.LevelSequenceRec[size]];
state.slave _ NEW[Ports.LevelSequenceRec[size]];
} ELSE state _ NARROW[oldStateAny];
state.ck _ p[Ports.PortIndex[cellType.public, "CK"]];
state.in _ p[Ports.PortIndex[cellType.public, "D"]];
state.out _ p[Ports.PortIndex[cellType.public, "Q"]];
state.out.d _ drive;
Ports.SetLS[state.master, X];
Ports.SetLS[state.slave, X];
Ports.SetLS[state.out.ls, X];
stateAny _ state;
};

DPEdgeFFSeqSimple: Rosemary.EvalProc = {
state: DPEdgeFFSeqState _ NARROW[stateAny];
IF ~clockEval THEN {
SELECT state.ck.l FROM
L => Ports.CopyLS[from: state.in.ls, to: state.master];
H => Ports.CopyLS[from: state.master, to: state.slave];
ENDCASE => {
IF state.slave#state.master THEN Ports.SetLS[state.slave, X];
IF state.master#state.in.ls THEN Ports.SetLS[state.master, X];
};
};
Ports.CopyLS[from: state.slave, to: state.out.ls];
};
DPInvName: Rope.ROPE = Rosemary.Register[roseClassName: "DPInvSeq", init: DPInvSeqInit, evalSimple: DPInvSeqSimple];

DPInvSeqState: TYPE = REF DPInvSeqStateRec;
DPInvSeqStateRec: TYPE = RECORD [
in0, out0: Ports.Port];

DPInvSeqInit: Rosemary.InitProc = {
state: DPInvSeqState _ IF oldStateAny=NIL THEN NEW[DPInvSeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.out0 _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out0.d _ drive;
stateAny _ state;
};

DPInvSeqSimple: Rosemary.EvalProc = {
state: DPInvSeqState _ NARROW[stateAny];
Ports.NotLS[state.in0.ls, state.out0.ls];
};
DPAnd2Name: Rope.ROPE = Rosemary.Register[roseClassName: "DPAnd2Seq", init: DPAnd2SeqInit, evalSimple: DPAnd2SeqSimple];

DPAnd2SeqState: TYPE = REF DPAnd2SeqStateRec;
DPAnd2SeqStateRec: TYPE = RECORD [
in0, en, out0: Ports.Port];

DPAnd2SeqInit: Rosemary.InitProc = {
state: DPAnd2SeqState _ IF oldStateAny=NIL THEN NEW[DPAnd2SeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.en _ p[Ports.PortIndex[cellType.public, "en"]];
state.out0 _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out0.d _ drive;
stateAny _ state;
};

DPAnd2SeqSimple: Rosemary.EvalProc = {
state: DPAnd2SeqState _ NARROW[stateAny];
SELECT TRUE FROM
state.en.l=H => Ports.CopyLS[state.in0.ls, state.out0.ls];
state.en.l=L => Ports.SetLS[state.out0.ls, L];
state.en.l=X => Ports.SetLS[state.out0.ls, X];
ENDCASE => ERROR;
};
DPNor2Name: Rope.ROPE = Rosemary.Register[roseClassName: "DPNor2Seq", init: DPNor2SeqInit, evalSimple: DPNor2SeqSimple];

DPNor2SeqState: TYPE = REF DPNor2SeqStateRec;
DPNor2SeqStateRec: TYPE = RECORD [
in0, in1, out0: Ports.Port];

DPNor2SeqInit: Rosemary.InitProc = {
state: DPNor2SeqState _ IF oldStateAny=NIL THEN NEW[DPNor2SeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.in1 _ p[Ports.PortIndex[cellType.public, "in1"]];
state.out0 _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out0.d _ drive;
stateAny _ state;
};

DPNor2SeqSimple: Rosemary.EvalProc = {
state: DPNor2SeqState _ NARROW[stateAny];
FOR index: NAT IN [0..state.in0.ls.size) DO
state.out0.ls[index] _ SELECT TRUE FROM
state.in0.ls[index]=L AND state.in1.ls[index]=L => H,
state.in0.ls[index]=H OR state.in1.ls[index]=H => L,
ENDCASE => X;
ENDLOOP;
};
DPWireOrName: Rope.ROPE = Rosemary.Register[roseClassName: "DPWireOrSeq", init: DPWireOrSeqInit, evalSimple: DPWireOrSeqSimple];

DPWireOrSeqState: TYPE = REF DPWireOrSeqStateRec;
DPWireOrSeqStateRec: TYPE = RECORD [
in, out: Ports.Port,
size: NAT];

DPWireOrSeqInit: Rosemary.InitProc = {
state: DPWireOrSeqState;
IF oldStateAny=NIL THEN {
state _ NEW[DPWireOrSeqStateRec];
state.size _ Ports.Size[p[Ports.PortIndex[cellType.public, "in"]]];
} ELSE state _ NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in"]];
state.out _ p[Ports.PortIndex[cellType.public, "out"]];
stateAny _ state;
};

DPWireOrSeqSimple: Rosemary.EvalProc = {
state: DPWireOrSeqState _ NARROW[stateAny];
state.out.d _ none;
FOR i: NAT IN [0..state.size) DO
IF state.in.ls[i] = H THEN {state.out.l _ L; state.out.d _ drive; EXIT};
IF state.in.ls[i] = X THEN {state.out.l _ X; state.out.d _ drive; EXIT};
ENDLOOP;
};

DPWireOrTermName: Rope.ROPE = Rosemary.Register[roseClassName: "DPWireOrTerm", init: DPWireOrTermInit, evalSimple: DPWireOrTermSimple];

DPWireOrTermState: TYPE = REF DPWireOrTermStateRec;
DPWireOrTermStateRec: TYPE = RECORD [out: Ports.Port];

DPWireOrTermInit: Rosemary.InitProc = {
state: DPWireOrTermState _ IF oldStateAny=NIL THEN NEW[DPWireOrTermStateRec] ELSE NARROW[oldStateAny];
stateAny _ state;
};

DPWireOrTermSimple: Rosemary.EvalProc = {
state: DPWireOrTermState _ NARROW[stateAny];
state.out.l _ H;
state.out.d _ driveWeak;
};

DPXOrName: Rope.ROPE = Rosemary.Register[roseClassName: "DPXOrSeq", init: DPXOrSeqInit, evalSimple: DPXOrSeqSimple];

DPXOrSeqState: TYPE = REF DPXOrSeqStateRec;
DPXOrSeqStateRec: TYPE = RECORD [
in0, in1, out: Ports.Port];

DPXOrSeqInit: Rosemary.InitProc = {
state: DPXOrSeqState _ IF oldStateAny=NIL THEN NEW[DPXOrSeqStateRec] ELSE NARROW[oldStateAny];
state.in0 _ p[Ports.PortIndex[cellType.public, "in0"]];
state.in1 _ p[Ports.PortIndex[cellType.public, "in1"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPXOrSeqSimple: Rosemary.EvalProc = {
state: DPXOrSeqState _ NARROW[stateAny];
FOR index: NAT IN [0..state.in0.ls.size) DO
state.out.ls[index] _ SELECT TRUE FROM
state.in0.ls[index]=X OR state.in1.ls[index]=X => X,
state.in0.ls[index] = state.in1.ls[index] => L,
ENDCASE => H;
ENDLOOP;
};

DPSCTriName: Rope.ROPE = Rosemary.Register[roseClassName: "DPSCTriSeq", init: DPSCTriSeqInit, evalSimple: DPSCTriSeqSimple];

DPSCTriSeqState: TYPE = REF DPSCTriSeqStateRec;
DPSCTriSeqStateRec: TYPE = RECORD [
in, out, en, dis: Ports.Port];

DPSCTriSeqInit: Rosemary.InitProc = {
state: DPSCTriSeqState _ IF oldStateAny=NIL THEN NEW[DPSCTriSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in"]];
state.out _ p[Ports.PortIndex[cellType.public, "out"]];
state.en _ p[Ports.PortIndex[cellType.public, "en"]];
state.dis _ p[Ports.PortIndex[cellType.public, "dis"]];
stateAny _ state;
};

DPSCTriSeqSimple: Rosemary.EvalProc = {
state: DPSCTriSeqState _ NARROW[stateAny];
Ports.CopyLS[state.in.ls, state.out.ls];
state.out.d _ IF state.en.l=H AND state.dis.l=L THEN drive ELSE none;
};
DPSCBufName: Rope.ROPE = Rosemary.Register[roseClassName: "DPSCBufSeq", init: DPBufSeqInit, evalSimple: DPBufSeqSimple];

DPBufSeqState: TYPE = REF DPBufSeqStateRec;
DPBufSeqStateRec: TYPE = RECORD [
in, out: Ports.Port];

DPBufSeqInit: Rosemary.InitProc = {
state: DPBufSeqState _ IF oldStateAny=NIL THEN NEW[DPBufSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in0"]];
state.out _ p[Ports.PortIndex[cellType.public, "out0"]];
state.out.d _ drive;
stateAny _ state;
};

DPBufSeqSimple: Rosemary.EvalProc = {
state: DPBufSeqState _ NARROW[stateAny];
Ports.CopyLS[state.in.ls, state.out.ls];
};
DPCBufName: Rope.ROPE = Rosemary.Register[roseClassName: "CBufSeq", init: DPCBufSeqInit, evalSimple: DPCBufSeqSimple];

DPCBufSeqState: TYPE = REF DPCBufSeqStateRec;
DPCBufSeqStateRec: TYPE = RECORD [
in, out, en: Ports.Port];

DPCBufSeqInit: Rosemary.InitProc = {
state: DPCBufSeqState _ IF oldStateAny=NIL THEN NEW[DPCBufSeqStateRec] ELSE NARROW[oldStateAny];
state.in _ p[Ports.PortIndex[cellType.public, "in"]];
state.out _ p[Ports.PortIndex[cellType.public, "out"]];
state.en _ p[Ports.PortIndex[cellType.public, "en"]];
stateAny _ state;
};

DPCBufSeqSimple: Rosemary.EvalProc = {
state: DPCBufSeqState _ NARROW[stateAny];
Ports.CopyLS[state.in.ls, state.out.ls];
state.out.d _ IF state.en.l=H THEN drive ELSE none;
};
DPCRegName: Rope.ROPE = Rosemary.Register[roseClassName: "CRegSeq", init: DPCRegSeqInit, evalSimple: DPCRegSeqSimple];

DPCRegSeqState: TYPE = REF DPCRegSeqStateRec;
DPCRegSeqStateRec: TYPE = RECORD [
nC, C, Sel, Q: Ports.Port,
slave, nSlave: Ports.LevelSequence,
size: NAT];

DPCRegSeqInit: Rosemary.InitProc = {
state: DPCRegSeqState;
IF oldStateAny=NIL THEN {
state _ NEW[DPCRegSeqStateRec];
state.size _ Ports.Size[p[Ports.PortIndex[cellType.public, "C"]]];
state.slave _ NEW[Ports.LevelSequenceRec[state.size]];
state.nSlave _ NEW[Ports.LevelSequenceRec[state.size]];
} ELSE state _ NARROW[oldStateAny];
state.nC _ p[Ports.PortIndex[cellType.public, "nC"]];
state.C _ p[Ports.PortIndex[cellType.public, "C"]];
state.Sel _ p[Ports.PortIndex[cellType.public, "Sel"]];
state.Q _ p[Ports.PortIndex[cellType.public, "Q"]];
state.Q.d _ drive;
Ports.SetLS[state.slave, X];
Ports.SetLS[state.nSlave, X];
Ports.SetLS[state.Q.ls, X];
stateAny _ state;
};

DPCRegSeqSimple: Rosemary.EvalProc = {
state: DPCRegSeqState _ NARROW[stateAny];
IF state.Sel.l = H THEN {
FOR i: NAT IN [0..state.size) DO
SELECT TRUE FROM
state.C.ls[i]=H AND state.nC.ls[i]=H => { -- read
IF state.slave[i]=H THEN state.nC.ls[i] _ L;
IF state.nSlave[i]=H THEN state.C.ls[i] _ L;
};
state.C.ls[i]=L AND state.nC.ls[i]=H => { -- write 0
state.slave[i] _ L;
state.nSlave[i] _ H;
};
state.C.ls[i]=H AND state.nC.ls[i]=L => { -- write 1
state.slave[i] _ H;
state.nSlave[i] _ L;
};
ENDCASE => { -- LL, LX, XL, HX, XH, XX
state.slave[i] _ X;
state.nSlave[i] _ X;
};
ENDLOOP;
FOR i: NAT IN [0..state.size) DO
state.C.ds[i] _ IF state.nSlave[i] = H THEN drive ELSE driveWeak;
state.nC.ds[i] _ IF state.slave[i] = H THEN drive ELSE driveWeak;
ENDLOOP;
} ELSE {
FOR i: NAT IN [0..state.size) DO
Ports.PutDriveSequence[state.C, i, none];
Ports.PutDriveSequence[state.nC, i, none];
ENDLOOP
};
Ports.CopyLS[state.slave, state.Q.ls];
};
DPDPRamTopWEnName: Rope.ROPE = Rosemary.Register[roseClassName: "DPDPRamTopWEnSeq", init: DPDPRamTopWEnSeqInit, evalSimple: DPDPRamTopWEnSeqSimple];

DPDPRamTopWEnSeqState: TYPE = REF DPDPRamTopWEnSeqStateRec;
DPDPRamTopWEnSeqStateRec: TYPE = RECORD [
DIn, WrEn, nPChg, nB, B: Ports.Port];

DPDPRamTopWEnSeqInit: Rosemary.InitProc = {
state: DPDPRamTopWEnSeqState _ IF oldStateAny=NIL THEN NEW[DPDPRamTopWEnSeqStateRec] ELSE NARROW[oldStateAny];
state.DIn _ p[Ports.PortIndex[cellType.public, "DIn"]];
state.WrEn _ p[Ports.PortIndex[cellType.public, "WrEn"]];
state.nPChg _ p[Ports.PortIndex[cellType.public, "nPChg"]];
state.nB _ p[Ports.PortIndex[cellType.public, "nB"]];
state.B _ p[Ports.PortIndex[cellType.public, "B"]];
stateAny _ state;
};

DPDPRamTopWEnSeqSimple: Rosemary.EvalProc = {
state: DPDPRamTopWEnSeqState _ NARROW[stateAny];
IF state.nPChg.l=L THEN {
Ports.SetLS[state.nB.ls, H];
Ports.SetLS[state.B.ls, H];
state.nB.d _ driveWeak;
state.B.d _ driveWeak;
};
IF state.WrEn.l=H THEN {
Ports.NotLS[state.DIn.ls, state.nB.ls];
Ports.CopyLS[state.DIn.ls, state.B.ls];
state.nB.d _ drive;
state.B.d _ drive;
};
IF state.WrEn.l#H AND state.nPChg.l#L THEN {
state.nB.d _ none;
state.B.d _ none;
};
};
DPDPRamTopName: Rope.ROPE = Rosemary.Register[roseClassName: "DPDPRamTopSeq", init: DPDPRamTopSeqInit, evalSimple: DPDPRamTopSeqSimple];

DPDPRamTopSeqState: TYPE = REF DPDPRamTopSeqStateRec;
DPDPRamTopSeqStateRec: TYPE = RECORD [
DIn, nB, B: Ports.Port];

DPDPRamTopSeqInit: Rosemary.InitProc = {
state: DPDPRamTopSeqState _ IF oldStateAny=NIL THEN NEW[DPDPRamTopSeqStateRec] ELSE NARROW[oldStateAny];
state.DIn _ p[Ports.PortIndex[cellType.public, "DIn"]];
state.nB _ p[Ports.PortIndex[cellType.public, "nB"]];
state.B _ p[Ports.PortIndex[cellType.public, "B"]];
state.nB.d _ drive;
state.B.d _ drive;
stateAny _ state;
};

DPDPRamTopSeqSimple: Rosemary.EvalProc = {
state: DPDPRamTopSeqState _ NARROW[stateAny];
Ports.NotLS[state.DIn.ls, state.nB.ls];
Ports.CopyLS[state.DIn.ls, state.B.ls];
};
DPDPRamBitName: Rope.ROPE = Rosemary.Register[roseClassName: "DPDPRamBitSeq", init: DPDPRamBitSeqInit, evalSimple: DPDPRamBitSeqSimple];

DPDPRamBitSeqState: TYPE = REF DPDPRamBitSeqStateRec;
DPDPRamBitSeqStateRec: TYPE = RECORD [
RB, nB, B, Wr, Rd: Ports.Port,
slave, nSlave: Ports.LevelSequence,
size: NAT];

DPDPRamBitSeqInit: Rosemary.InitProc = {
state: DPDPRamBitSeqState;
IF oldStateAny=NIL THEN {
state _ NEW[DPDPRamBitSeqStateRec];
state.size _ Ports.Size[p[Ports.PortIndex[cellType.public, "RB"]]];
state.slave _ NEW[Ports.LevelSequenceRec[state.size]];
state.nSlave _ NEW[Ports.LevelSequenceRec[state.size]];
} ELSE state _ NARROW[oldStateAny];
state.RB _ p[Ports.PortIndex[cellType.public, "RB"]];
state.nB _ p[Ports.PortIndex[cellType.public, "nB"]];
state.B _ p[Ports.PortIndex[cellType.public, "B"]];
state.Wr _ p[Ports.PortIndex[cellType.public, "Wr"]];
state.Rd _ p[Ports.PortIndex[cellType.public, "Rd"]];
Ports.SetLS[state.slave, X];
Ports.SetLS[state.nSlave, X];
CoreProperties.PutCellTypeProp[cellType, RosemaryUser.stateToMaxCharsProcProp, NEW[RosemaryUser.StateToMaxCharsProc _ DPDPRamStateToMaxChars]];
CoreProperties.PutCellTypeProp[cellType, RosemaryUser.stateToRopeProcProp, NEW[RosemaryUser.StateToRopeProc _ DPDPRamStateToRope]];
stateValue _ state.slave;
stateAny _ state;
};

DPDPRamBitSeqSimple: Rosemary.EvalProc = {
state: DPDPRamBitSeqState _ NARROW[stateAny];
IF state.Wr.l = H THEN {
FOR i: NAT IN [0..state.size) DO
SELECT TRUE FROM
state.B.ls[i]=H AND state.nB.ls[i]=H => { -- read
IF state.slave[i]=H THEN state.nB.ls[i] _ L;
IF state.nSlave[i]=H THEN state.B.ls[i] _ L;
};
state.B.ls[i]=L AND state.nB.ls[i]=H => { -- write 0
state.slave[i] _ L;
state.nSlave[i] _ H;
};
state.B.ls[i]=H AND state.nB.ls[i]=L => { -- write 1
state.slave[i] _ H;
state.nSlave[i] _ L;
};
ENDCASE => { -- LL, LX, XL, HX, XH, XX
state.slave[i] _ X;
state.nSlave[i] _ X;
};
ENDLOOP;
Ports.CopyLS[state.slave, state.B.ls];
Ports.CopyLS[state.nSlave, state.nB.ls];
FOR i: NAT IN [0..state.size) DO
state.B.ds[i] _ IF state.nSlave[i] = H THEN drive ELSE driveWeak;
state.nB.ds[i] _ IF state.slave[i] = H THEN drive ELSE driveWeak;
ENDLOOP;
} ELSE {
FOR i: NAT IN [0..state.size) DO
Ports.PutDriveSequence[state.B, i, none];
Ports.PutDriveSequence[state.nB, i, none];
ENDLOOP;
};
Ports.CopyLS[state.nSlave, state.RB.ls];
FOR i: NAT IN [0..state.size) DO
state.RB.ds[i] _ IF state.RB.ls[i]=L AND state.Rd.l=H THEN drive ELSE none;
ENDLOOP;
stateValue _ state.slave;
};

DPDPRamStateToMaxChars: RosemaryUser.StateToMaxCharsProc = {
state: DPDPRamBitSeqState _ NARROW[stateAny];
maxChars _ (state.size+3)/4 + 1;   --round to max number of hex digits
};

DPDPRamStateToRope: RosemaryUser.StateToRopeProc = {
rope _ Ports.LSToRope[value];
};


DPDPRamBotName: Rope.ROPE = Rosemary.Register[roseClassName: "DPDPRamBotSeq", init: DPDPRamBotSeqInit, evalSimple: DPDPRamBotSeqSimple];

DPDPRamBotSeqState: TYPE = REF DPDPRamBotSeqStateRec;
DPDPRamBotSeqStateRec: TYPE = RECORD [
RB, DOut: Ports.Port];

DPDPRamBotSeqInit: Rosemary.InitProc = {
state: DPDPRamBotSeqState _ IF oldStateAny=NIL THEN NEW[DPDPRamBotSeqStateRec] ELSE NARROW[oldStateAny];
state.RB _ p[Ports.PortIndex[cellType.public, "RB"]];
state.DOut _ p[Ports.PortIndex[cellType.public, "DOut"]];
Ports.SetLS[state.RB.ls, H];
state.RB.d _ driveWeak;
state.DOut.d _ drive;
stateAny _ state;
};

DPDPRamBotSeqSimple: Rosemary.EvalProc = {
state: DPDPRamBotSeqState _ NARROW[stateAny];
Ports.NotLS[state.RB.ls, state.DOut.ls];
Ports.SetLS[state.RB.ls, H];
};
DPDecoderName: Rope.ROPE = Rosemary.Register[roseClassName: "DPDecoderSeq", init: DPDecoderSeqInit, evalSimple: DPDecoderSeqSimple];

DPDecoderSeqState: TYPE = REF DPDecoderSeqStateRec;
DPDecoderSeqStateRec: TYPE = RECORD [
RA, WA, wEn, CK, Rd, Wr: Ports.Port,
size: NAT];

DPDecoderSeqInit: Rosemary.InitProc = {
state: DPDecoderSeqState _ IF oldStateAny=NIL THEN NEW[DPDecoderSeqStateRec] ELSE NARROW[oldStateAny];
state.RA _ p[Ports.PortIndex[cellType.public, "RA"]];
state.WA _ p[Ports.PortIndex[cellType.public, "WA"]];
state.wEn _ p[Ports.PortIndex[cellType.public, "wEn"]];
state.CK _ p[Ports.PortIndex[cellType.public, "CK"]];
state.Rd _ p[Ports.PortIndex[cellType.public, "Rd"]];
state.Wr _ p[Ports.PortIndex[cellType.public, "Wr"]];
state.Rd.d _ drive;
state.Wr.d _ drive;
stateAny _ state;
};

DPDecoderSeqSimple: Rosemary.EvalProc = {
state: DPDecoderSeqState _ NARROW[stateAny];
IF Ports.HasX[state.RA.ls] THEN Ports.SetLS[state.Rd.ls, X] ELSE {
Ports.SetLS[state.Rd.ls, L];
Ports.PutLevelSequence[state.Rd, Ports.LSToC[state.RA.ls], H];
};
IF state.wEn.l = X OR state.CK.l = X OR Ports.HasX[state.WA.ls] THEN Ports.SetLS[state.Wr.ls, X] ELSE {
Ports.SetLS[state.Wr.ls, L];
IF state.wEn.l = H AND state.CK.l = L THEN Ports.PutLevelSequence[state.Wr, Ports.LSToC[state.WA.ls], H];
};
};
DataPath.RegisterDataPathSpec["TR72", NEW[DataPath.DPSpecRec _ [
layDWidth:	72*	CMosB.lambda,
schDWidth:	9*	4*	CMosB.lambda,
layBusW:			8*	CMosB.lambda,
schBusW:			4*	CMosB.lambda,
metPitch:			8*	CMosB.lambda,
met2Pitch:		8*	CMosB.lambda,
leftTail:			4*	CMosB.lambda,	-- to center of 0th bus
rightTail:			4*	CMosB.lambda,	-- metPitch-leftTail
initialYSize:		3*	CMosB.lambda,	-- for channel use (=>top
gndBus:			0,
vddBus:			1,
pwrW:			5*	CMosB.lambda,
metW:				3*	CMosB.lambda,
met2W:			4*	CMosB.lambda,
polW:				2*	CMosB.lambda,
difW:				2*	CMosB.lambda,
pinSize:			2*	CMosB.lambda ]]];


END.

pTRDataPathImpl.mesa
Copyright c 1985 by Xerox Corporation.  All rights reserved.
Don Curry, November 11, 1987 1:36:42 am PST
Last Edited by: Gasbarro February 15, 1988 10:56:21 am PST

EXPORTS
DPEdgeFF, DPEdgeFFTop
DPInv
DPAnd2
DPNor2
DPWireOr
DPWireOrTerm
DPXOr
DPSCTri
DPSCBuf
CBuf
CReg
DPDPRamTopWEn
DPDPRamTop
DPDPRamBit
DPDPRamBot
DPDecoder

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