PCMapCacheProg.mesa
Copyright Ó 1988 by Xerox Corporation. All rights reserved.
Created by Louis Monier, May 4, 1988 11:38:06 am PDT
This module changes the Atom which contains the program to send the Data
DIRECTORY
Atom, BitOps; 
PCMapCacheProg: CEDAR PROGRAM
IMPORTS Atom, BitOps
EXPORTS
~ BEGIN
Service Types
QWord: TYPE = ARRAY [0 .. 2) OF CARD;
Service Procs
Q: PROC [c: QWord] RETURNS [rc: REF ANY] = {rc ← NEW[QWord ← c]};
C: PROC [c: CARD] RETURNS [rc: REF ANY] = {rc ← NEW[CARD ← LOOPHOLE[c]]};
B: PROC [c: CARDINAL] RETURNS [rc: REF ANY] = {rc ← NEW[CARDINAL ← c]};
AdDBus: PROC [bd,hyb,Int,ci,pth: CARDINAL 𡤀] RETURNS [ad: CARDINAL 𡤀] ~ {
Address in the DBus is :
<BoardNum:4><HybridNum:4><InterfaceNum:3><ChipNum:2><PathNum:3>
<ChipNum>=0 is for BIC
ad ← BitOps.WShift[bd,12]+BitOps.WShift[hyb,8];
ad ← ad+BitOps.WShift[Int,5]+BitOps.WShift[ci,3]+pth;
};
IdCte: PROC [t,v:CARDINAL] RETURNS [id:CARDINAL] ~ {
The structure of the Identificator is "0101 cccc ccrr rrrr"
cccccc is the Type, rrrrrr is the Version
id ← 5000H + BitOps.WShift[t,6] + v;
};
The Program Starts Here
Atom.PutProp[$PCEmul, $PKList, LIST[
$Init, -- initialize D Bus signals
$ResetOn,
Arbiter, BICs, and DynaBus Exerciser
These chips' DBus register initialization requirements need not be met in this simulation, because these chips are modelled to have plausible default values for these registers. (Right?)
Map Cache
LIST[$SendDBusAddress, B[AdDBus[bd:0, hyb:2, Int:1, ci:1, pth:0]]], -- chipID
LIST[$ReadDBusAndCheck, C[IdCte[t:9, v:0]], B[16]],
LIST[$SendDBusAddress, B[AdDBus[bd:0, hyb:2, Int:1, ci:1, pth:1]]], -- devID
LIST[$SendDBusData, C[40], B[10]], -- devID = 40
LIST[$SendDBusAddress, B[AdDBus[bd:0, hyb:2, Int:0, ci:1, pth:4]]], -- unused
  -- avoid harmful effects of DShiftCK glitch; 5-1-88.
$ResetOff,  -- after this, the D Bus is no longer used.
$Nop,
LIST[$Jump,$Nop],
]];
END.