DIRECTORY
      Atom, DynaBusInterface, Rope;	
      
DynDDCProg: CEDAR PROGRAM
IMPORTS  Atom
EXPORTS 
~ BEGIN
Quad: TYPE = DynaBusInterface.Quad;
Cmd: TYPE = DynaBusInterface.Cmd;

L: PROC [c: BOOL] RETURNS [rc: REF ANY] = {rc _ NEW[BOOL _ c]};
C: PROC [c: CARD] RETURNS [rc: REF ANY] = {rc _ NEW[CARD _ c]};
Q: PROC [c: Quad] RETURNS [rc: REF ANY] = {rc _ NEW[Quad _ c]};
Com: PROC [c: Cmd] RETURNS [rc: REF ANY] = {rc _ NEW[Cmd _ c]};
R: PROC [c: Rope.ROPE] RETURNS [rc: REF ANY] = {rc _ NEW[Rope.ROPE _ c]};


Atom.PutProp[$Simul2Sender, $PKList, LIST[
  $Init,
  $StartStop,
  $ReceiveAll,
  LIST[$Wait, C[1110]],		-- for waiting for DBus initialization

  LIST[$IOWrite0, C[1], L[TRUE], L[TRUE], C[0],C[28],C[28],C[28],C[22],C[22]],
  $WaitMsgSent,
  LIST[$Wait, C[9]],  -- for snooping
  LIST[$SendShOw,R["SO"]], 
  $WaitMsgReceived, -- for the Echo
  $WaitReply,

  LIST[$IOWrite1, C[1],C[10],C[0],C[0]],
  $WaitMsgSent,
  $WaitMsgReceived, -- for the Echo
  $WaitReply,

  LIST[$IOWrite2, C[1],C[10],C[0]],
  $WaitMsgSent,
  $WaitMsgReceived, -- for the Echo
  $WaitReply,

  LIST[$WriteBlockRqst, Q[[0,0,0,0]],Q[[3,3,3,3]],Q[[2,2,2,2]],Q[[1,1,1,1]],Q[[0,0,0,0]]],
  $WaitMsgSent,
  $WaitMsgReceived, -- for the Echo
  $WaitReply,

  LIST[$WriteBlockRqst, Q[[0,0,0,0]],Q[[0,0,0,0]],Q[[1,1,1,1]],Q[[2,2,2,2]],Q[[3,3,3,3]]],
  $WaitMsgSent,
  $WaitMsgReceived, -- for the Echo
  $WaitReply,

  LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0000H ]],	-- address
	Q[[ 0001H, 0203H, 0405H, 0607H ]],	-- data
	Q[[ 0809H, 0A0BH, 0C0DH, 0E0FH ]],	-- data
	Q[[ 1011H, 1213H, 1415H, 1617H ]],	-- data
	Q[[ 1819H, 1A1BH, 1C1DH, 1E1FH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************

LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0008H ]],	-- address
	Q[[ 2021H, 2223H, 2425H, 2627H ]],	-- data
	Q[[ 2829H, 2A2BH, 2C2DH, 2E2FH ]],	-- data
	Q[[ 3031H, 3233H, 3435H, 3637H ]],	-- data
	Q[[ 3839H, 3A3BH, 3C3DH, 3E3FH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0010H ]],	-- address
	Q[[ 4041H, 4243H, 4445H, 4647H ]],	-- data
	Q[[ 4849H, 4A4BH, 4C4DH, 4E4FH ]],	-- data
	Q[[ 5051H, 5253H, 5455H, 5657H ]],	-- data
	Q[[ 5859H, 5A5BH, 5C5DH, 5E5FH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0018H ]],	-- address
	Q[[ 6061H, 6263H, 6465H, 6667H ]],	-- data
	Q[[ 6869H, 6A6BH, 6C6DH, 6E6FH ]],	-- data
	Q[[ 7071H, 7273H, 7475H, 7677H ]],	-- data
	Q[[ 7879H, 7A7BH, 7C7DH, 7E7FH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
  LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0020H ]],	-- address
	Q[[ 8081H, 8283H, 8485H, 8687H ]],	-- data
	Q[[ 8889H, 8A8BH, 8C8DH, 8E8FH ]],	-- data
	Q[[ 9091H, 9293H, 9495H, 9697H ]],	-- data
	Q[[ 9899H, 9A9BH, 9C9DH, 9E9FH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************

LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0028H ]],	-- address
	Q[[0A0A1H,0A2A3H,0A4A5H,0A6A7H ]],	-- data
	Q[[0A8A9H,0AAABH,0ACADH,0AEAFH ]],	-- data
	Q[[0B0B1H,0B2B3H,0B4B5H,0B6B7H ]],	-- data
	Q[[0B8B9H,0BABBH,0BCBDH,0BEBFH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0030H ]],	-- address
	Q[[0C0C1H,0C2C3H,0C4C5H,0C6C7H ]],	-- data
	Q[[0C8C9H,0CACBH,0CCCDH,0CECFH ]],	-- data
	Q[[0D0D1H,0D2D3H,0D4D5H,0D6D7H ]],	-- data
	Q[[0D8D9H,0DADBH,0DCDDH,0DEDFH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
LIST[$WriteBlockRqst,			-- initialize memory
	Q[[ 0,     0,     0000H, 0038H ]],	-- address
	Q[[0E0E1H,0E2E3H,0E4E5H,0E6E7H ]],	-- data
	Q[[0E8E9H,0EAEBH,0ECEDH,0EEEFH ]],	-- data
	Q[[0F0F1H,0F2F3H,0F4F5H,0F6F7H ]],	-- data
	Q[[0F8F9H,0FAFBH,0FCFDH,0FEFFH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $WriteBlockRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- framePtrBase _ 0
	Q[[ 0,     0,     0020H, 0A80H ]],	-- address
	Q[[ 0,     0,     0000H, 0000H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- framePtrLimit _ 1000H
	Q[[ 0,     0,     0020H, 0A81H ]],	-- address
	Q[[ 0,     0,     0000H, 1000H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- bitsPerPixel _ 3 (meaning 8 bits/pixel)
	Q[[ 0,     0,     0020H, 0A83H ]],	-- address
	Q[[ 0,     0,     0000H, 0003H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- intOffset _ 0DH
	Q[[ 0,     0,     0020H, 0A88H ]],	-- address
	Q[[ 0,     0,     0000H, 000DH ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOReadRqst,			-- read back framePtrBase
	Q[[ 0,     0,     0020H, 0A80H ]]],	-- address
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOReadRqst
  LIST[$WaitIOReadRplyandCheck,
	Q[[ 0,     0,     0020H, 0A80H ]],
	Q[[ 0,     0,     0000H, 0000H ]]],	-- data

  LIST[$IOReadRqst,			-- read back intOffset
	Q[[ 0,     0,     0020H, 0A88H ]]],	-- address
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOReadRqst
  LIST[$WaitIOReadRplyandCheck,
	Q[[ 0,     0,     0020H, 0A88H ]],
	Q[[ 0,     0,     0000H, 000DH ]]],	-- data
  LIST[$IOWriteRqst,			-- vGen[0] _ 07FFC00
	Q[[ 0,     0,     0020H, 0A40H ]],	-- address
	Q[[ 0,     0,     007FH,0FC00H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- vGen[1] _ 0BFE000
	Q[[ 0,     0,     0020H, 0A41H ]],	-- address
	Q[[ 0,     0,     00BFH,0E000H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************

  LIST[$IOWriteRqst,			-- vGen[2] _ 0FFFC01
	Q[[ 0,     0,     0020H, 0A42H ]],	-- address
	Q[[ 0,     0,     00FFH,0FC01H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- vGen[3] _ 0FFFC00
	Q[[ 0,     0,     0020H, 0A43H ]],	-- address
	Q[[ 0,     0,     00FFH,0FC00H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOReadRqst,			-- first clear interrupts
	Q[[ 0,     0,     0020H, 0A82H ]]],	-- address
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOReadRqst
  $WaitReply,	-- don't check result, which should be X's
  LIST[$IOWriteRqst,			-- intMask _ 4H; (enable only int 0)
	Q[[ 0,     0,     0020H, 0A82H ]],	-- address
	Q[[ 0,     0,     0000H, 0004H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$IOWriteRqst,			-- vGenEn _ 1; (start microcode)
	Q[[ 0,     0,     0020H, 0A87H ]],	-- address
	Q[[ 0,     0,     0000H, 0001H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$WaitIOWRqstandCheck,		--  here's the interrupt.
	Q[[ 0,     0,     0010H, 000DH ]],	-- address
	Q[[ 0,     0,     0400H, 0000H ]]],	-- data (2^(31-reason))

  LIST[$IOWriteRply,	
	Q[[ 0,     0,     0010H, 000DH ]],
	Q[[ 0,     0,     0400H, 0000H ]]],
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRply

  LIST[$IOReadRqst,			-- read and clear interrupts
	Q[[ 0,     0,     0020H, 0A82H ]]],	-- address
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOReadRqst
  LIST[$WaitIOReadRplyandCheck,
	Q[[ 0,     0,     0020H, 0A82H ]],
	Q[[ 0,     0,     0000H, 0024H ]]],	-- data
  LIST[$IOWriteRqst,			-- rBRqstEn _ 1; (enable RBRqst's)
	Q[[ 0,     0,     0020H, 0A86H ]],	-- address
	Q[[ 0,     0,     0000H, 0001H ]]],	-- data
  $WaitMsgSent,
  $WaitMsgReceived,	-- echo of above $IOWriteRqst
  $WaitReply,	-- *************************************
  LIST[$WaitReadBlockRqstandCheck,		-- a RBRqst occurs.
	Q[[ 0,     0,     0000H, 0000H ]],	-- address
	Q[[ 0,     0,     0000H, 0000H ]]],	-- victim address (invalid)
  LIST[$WaitReadBlockRqstandCheck,		-- another RBRqst occurs.
	Q[[ 0,     0,     0000H, 0008H ]],	-- address
	Q[[ 0,     0,     0000H, 0000H ]]],	-- victim address (invalid)

  LIST[$WaitReadBlockRplyandCheck,		-- a RBRply occurs.
	Q[[ 0001H, 0203H, 0405H, 0607H ]],	-- data
	Q[[ 0809H, 0A0BH, 0C0DH, 0E0FH ]],	-- data
	Q[[ 1011H, 1213H, 1415H, 1617H ]],	-- data
	Q[[ 1819H, 1A1BH, 1C1DH, 1E1FH ]]],	-- data
  LIST[$WaitReadBlockRplyandCheck,		-- another RBRply occurs.
	Q[[ 2021H, 2223H, 2425H, 2627H ]],	-- data
	Q[[ 2829H, 2A2BH, 2C2DH, 2E2FH ]],	-- data
	Q[[ 3031H, 3233H, 3435H, 3637H ]],	-- data
	Q[[ 3839H, 3A3BH, 3C3DH, 3E3FH ]]],	-- data

  LIST[$WaitReadBlockRplyandCheck,		-- a RBRply occurs.
	Q[[ 4041H, 4243H, 4445H, 4647H ]],	-- data
	Q[[ 4849H, 4A4BH, 4C4DH, 4E4FH ]],	-- data
	Q[[ 5051H, 5253H, 5455H, 5657H ]],	-- data
	Q[[ 5859H, 5A5BH, 5C5DH, 5E5FH ]]],	-- data
  LIST[$WaitReadBlockRplyandCheck,		-- another RBRply occurs.
	Q[[ 6061H, 6263H, 6465H, 6667H ]],	-- data
	Q[[ 6869H, 6A6BH, 6C6DH, 6E6FH ]],	-- data
	Q[[ 7071H, 7273H, 7475H, 7677H ]],	-- data
	Q[[ 7879H, 7A7BH, 7C7DH, 7E7FH ]]],	-- data
  LIST[$WaitReadBlockRplyandCheck,		-- a RBRply occurs.
	Q[[ 8081H, 8283H, 8485H, 8687H ]],	-- data
	Q[[ 8889H, 8A8BH, 8C8DH, 8E8FH ]],	-- data
	Q[[ 9091H, 9293H, 9495H, 9697H ]],	-- data
	Q[[ 9899H, 9A9BH, 9C9DH, 9E9FH ]]],	-- data
  LIST[$WaitReadBlockRplyandCheck,		-- another RBRply occurs.
	Q[[0A0A1H,0A2A3H,0A4A5H,0A6A7H ]],	-- data
	Q[[0A8A9H,0AAABH,0ACADH,0AEAFH ]],	-- data
	Q[[0B0B1H,0B2B3H,0B4B5H,0B6B7H ]],	-- data
	Q[[0B8B9H,0BABBH,0BCBDH,0BEBFH ]]],	-- data

  LIST[$WaitReadBlockRplyandCheck,		-- a RBRply occurs.
	Q[[0C0C1H,0C2C3H,0C4C5H,0C6C7H ]],	-- data
	Q[[0C8C9H,0CACBH,0CCCDH,0CECFH ]],	-- data
	Q[[0D0D1H,0D2D3H,0D4D5H,0D6D7H ]],	-- data
	Q[[0D8D9H,0DADBH,0DCDDH,0DEDFH ]]],	-- data
  LIST[$WaitReadBlockRplyandCheck,		-- another RBRply occurs.
	Q[[0E0E1H,0E2E3H,0E4E5H,0E6E7H ]],	-- data
	Q[[0E8E9H,0EAEBH,0ECEDH,0EEEFH ]],	-- data
	Q[[0F0F1H,0F2F3H,0F4F5H,0F6F7H ]],	-- data
	Q[[0F8F9H,0FAFBH,0FCFDH,0FEFFH ]]],	-- data

  $Nop,
  LIST[$Jump, $Nop]

]];

END.


HDynDDCProg2.mesa
Copyright ำ 1988 by Xerox Corporation.  All rights reserved.
Created by Jean Gastinel, April 4, 1988 4:35:31 pm PDT
Bob Hagmann December 2, 1987 12:01:10 pm PST
Hoel, May 3, 1988 7:47:07 pm PDT

Hoel, April 8, 1988 8:06:51 pm PDT

Copied from DynDDCProg.mesa, May 3, 1988.  Alternate simulation file.
This file does a lot more RBRqsts than DynDDCProg, so it gives the Memory Controller a workout.  (Still, since there's only one bank, I can't saturate the bus.)  Jean Gastinel thought it would be interesting.
Changes:
Set framePtrLimit _ 1000H (not 10H) (in other words, infinity rather than 2 blocks.)
Initialize more memory blocks (8, not 2).
Check the reading of more memory blocks (8, not 2).
(In all, something like 124 memory blocks will be read -- until the FIFO is ``Full.'' However, none but the first eight blocks will be checked, and in fact none but the first eight blocks will have valid data.)

This module creates the Atom which contains the program for the DynaBus exerciser chip to send and receive DynaBus packets to test the display controller chip (DDC).

The Program Starts Here
			-- wish I could wait for $ResetOff instead.
First Initialize MemCtl Chip  (copied from /Dragon/Dragon7.0/SSMem/DynMemProg.mesa)

  LIST[$IOWriteRqst, Q[[0, 0, 0030H, 0400H]], Q[[0, 0, 0E19EH, 72D6H]]],
  LIST[$IOWriteRqst, Q[[0, 0, 0030H, 0401H]], Q[[0, 0, ****H, ****H]]],
  LIST[$IOWriteRqst, Q[[0, 0, 0030H, 0402H]], Q[[0, 0, ****H, ****H]]],
Then Initialize Memory Locations

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0000H ]]],
  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0008H ]]],

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0010H ]]],

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0018H ]]],

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0020H ]]],
  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0028H ]]],

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0030H ]]],

  LIST[$WaitWriteBlockRplyandCheck,
	Q[[ 0,     0,     0000H, 0038H ]]],



Then On to DDC:

Register Initialization

	(For the following commands, devID=0 and mode=kernel always.)

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A80H ]]],

  LIST[$WaitIOWRplytandCheck,
	Q[[ 0,     0,     0020H, 0A81H ]]],

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A83H ]]],

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A88H ]]],

Register Readback	-- just to show that IORRqst works


Microcode Initialization

World's dumbest microcode -- only generates one interrupt.
	00:  Jump 01;
	01:  Jump 02; Take8Cycles;
	02:  Jump 03; ProgInt;
	03:  Jump 03;

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A40H ]]],

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A41H ]]],
  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A42H ]]],

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A43H ]]],

Generate An Interrupt


  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A82H ]]],

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A87H ]]],


Read Block Requests

  LIST[$WaitIOWRplyandCheck,
	Q[[ 0,     0,     0020H, 0A86H ]]],


Don't check any more RBRqsts, because it's too hard to know how the RBRqsts and RBRply's will be interleaved.

	Q[[ 0,     0,     0000H, 0000H ]],        -- address (not checked.  why?)

	Q[[ 0,     0,     0000H, 0008H ]],        -- address (not checked.  why?)
	Q[[ 0,     0,     0000H, 0010H ]],        -- address (not checked.  why?)

	Q[[ 0,     0,     0000H, 0018H ]],        -- address (not checked.  why?)

	Q[[ 0,     0,     0000H, 0020H ]],        -- address (not checked.  why?)

	Q[[ 0,     0,     0000H, 0028H ]],        -- address (not checked.  why?)
	Q[[ 0,     0,     0000H, 0030H ]],        -- address (not checked.  why?)

	Q[[ 0,     0,     0000H, 0038H ]],        -- address (not checked.  why?)


Then Just Wait
Notes:

1.  For more information on what the atoms in the program list do, see:
[Dragon]<Dragon7.0>DynaBusInterface>Simul2SenderImpl.mesa.

Questions:

1.  What is the address range of DDC in the simulation?  00200800H - 00200BFFH.

2.  For $IOWriteRqst:
a.  Why not call it $IOWRqst?
b.  What is the mode bit? (I'd like mode = 0 = kernel, usually, but not always.)
c.  What is the devID?  (I'd guess devID = 1, based on the agreement with Jean of 4-13-88.)  (On second thought, I'd guess devID = 0, based on the agreement with Jean of 4-22-88.)
d.  What is the Reply/Shared bit's value?  (I don't really care; just curious.)

3.  May I also have:
a.  $IOWriteRply (i.e., $IOWRply)?
-  can program get the necessary bits from the corresponding IOWRqst?
b.  $WaitIOWRqstAndCheck?
-  let's think about what parameters are needed.
c.  $WaitReadBlockRqstAndCheck (i.e., $WaitRBRqstAndCheck)?
-  let's think about what parameters are needed.
d.  $ReadBlockRply
-  let's think about what parameters are needed.
e.  $WaitResetOff


4.  Can you ever be waiting for more than one thing, ready to take whatever happens first?  For example:
a.  After enabling vGenEn _ 1, we're waiting both for the reply and for the interrupt.
b.  After enabling rBRqstEn _ 1, we're waiting both for the reply and for the RBRqst's.

5.  Why is there a $WaitMsgSent?  (Why isn't it just part of the previous command?)

----------------------------

Change Log

4-24-88:  Tried filling in the program, using $opCodes supplied by Jean in msg of 4-20-88.
Still don't have:
$WaitIOWRplyandCheck	so substitute $WaitRply.
$IOWriteRply				so hope nobody cares that we can't do an interrupt acknowledge.
$WaitResetOff				so wait for a carefully chosen number of cycles.
$IOWriteRqstUserMode		so don't test yet
$IOReadRqstUserMode		so don't test yet
$RBRplyFault				so don't test yet
$IOWRplyFault				so don't test yet
Questions:
$$WaitReadBlockRplyandCheck	why not check address cycle too???
Progress:
Let memory addresses be 0H and 8H; see DynMemProg.mesa.
4-24-88:  Decided to wait 1110 cycles, not 110 cycles.
4-25-88:  Inserted MemCtl initialization stuff from:
/Dragon/Dragon7.0/SSMem/DynMemProg.mesa.
4-27-88:  Tried to use ordinary $IOWriteRqst instead of exotic ones for MemCtl, so I can specify the right DevNum.
4-29-88:  Oh, yes.  Read interrupt register, to clear interrupt state, before enabling int 0.  Also acknowledge interrupt after it happens.
5-2-88:  Changed microcode to wait longer before interrupting; workaround to avoid having to fix $WaitReply in Simul2SenderImpl now.
5-2-88:  Changed FramePtrBase to 0 (from 76543200H) and FramePtrLimit to 10H (from 76543210H).  (I had previously changed the memory address values elsewhere in the program, but not here.  Oops.)
5-3-88:  Oops!  Also have to change expected value of FramePtrBase when read back.  While we're at it, add another read back, intOffset.
---------------------------
5-3-88:  First revision of DynDDCProg2.
5-3-88:  Bug fix:  load fourth microcode word into location 3, not location2.

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