~
BEGIN
outf: IO.STREAM;
lineCount : CARD;
Variables for the Oracle File
nr:INT = 1; --number of colums in the right side of the line
nl:INT = 4; --number of colums in the left side of the line
NbRight : TYPE = [0..nr);
NbLeft : TYPE = [0..nl);
RightLine: TYPE = ARRAY NbRight OF Rope.ROPE;
LeftLine: TYPE = ARRAY NbLeft OF Rope.ROPE;
rl: RightLine;
ll: LeftLine;
comment: Rope.ROPE;
Special variables of the PC-Bus
Signal : TYPE = {T,F,X};
MDSerialIn,MDExecute,MDAddress : Signal;
MDShiftCK,MnDFreeze,MnDReset : Signal;
MDSerialOut: Signal;
IOWPC,IORPC,nIOWPC,nIORPC: Signal;
Address, DataIn, DataOut, dregister : INT; --negative Data & Address means X
Init:
PROC []
RETURNS [] ~ {
MDSerialIn ← X;
MDExecute ← X;
MDAddress ← X;
MDShiftCK ← X;
MnDFreeze ← T;
MnDReset ← F;
Address ← 0;
DataIn ← -1; --negative INT means X
DataOut ← -1;
IOWPC ← F;
IORPC ← F;
MDSerialOut ← F;
};
RopeFromSignal:
PROC [s: Signal]
RETURNS [r: Rope.
ROPE] ~ {
Convert a signal {F,T,X} into the corresponding Rope {0,1,X}
SELECT s
FROM
F => r ← "0";
T => r ← "1";
ENDCASE => r ← "X";
};
Inv:
PROC [s: Signal]
RETURNS [t: Signal] ~ {
t gets the invert of s
SELECT s
FROM
F => t ← T;
T => t ← F;
ENDCASE => t ← X;
};
Send:
PROC []
RETURNS [] ~ {
This Proc convert the variables into ropes rl[i] & ll[i] for generating the line
then call MergeOut for writing the line
Here send generate DataOut nIOWPC & nIORPC, and DataIn
nIOWPC ← Inv[IOWPC];
nIORPC ← Inv[IORPC];
IF Address >= 0 THEN ll[0] ← OracleGen.LExtend[OracleGen.Hex[Address],5]
ELSE ll[0] ← "XXXXX";
IF DataOut >= 0 THEN ll[1] ← OracleGen.LExtend[OracleGen.Hex[DataOut],2]
ELSE ll[1] ← "XX";
ll[1] ← Rope.Concat["XX",ll[1]];
ll[2] ← RopeFromSignal[nIOWPC];
ll[3] ← RopeFromSignal[nIORPC];
IF DataIn >= 0 THEN rl[0] ← OracleGen.LExtend[OracleGen.Hex[DataIn],2]
ELSE rl[0] ← "XX";
rl[0] ← Rope.Concat["XX",rl[0]];
MergeOut;
lineCount ← lineCount+ 1;
};
MergeOut:
PROC []
RETURNS [] ~ {
This proc merge into two Rope Right and Left different elements of the line
and write the result in the output stream
column : INT;
r : Rope.ROPE;
r ← " ";
FOR column
IN [0..nl)
DO r ← Rope.Cat[r,ll[column]," "];
ENDLOOP;
r ← Rope.Cat[r," | "];
FOR column
IN [0..nr)
DO r ← Rope.Cat[r,rl[column]," "];
ENDLOOP;
outf.PutF["%g -- %g %g \n",IO.rope[r],IO.rope[Convert.RopeFromInt[lineCount]],IO.rope[comment]];
comment ← ""
};
Write:
PROC [adrs :
INT,da :
INT]
RETURNS [] ~ {
IOWPC ← T;
DataOut ← da;
Address ← adrs;
Send;
IOWPC ← F;
DataOut ← -1;
Send;
comment ← " Write Data out";
};
ReadAndCheck:
PROC [adrs :
INT,da :
INT]
RETURNS [] ~ {
Address ← adrs;
Send;
IORPC ← T;
Send;
comment ← " ReadAndCheck Data";
DataIn ← da;
Send;
IORPC ← F;
DataIn ← -1;
Send;
};
AssembleDbus:
PROC []
RETURNS [da:
INT] ~ {
IF (MnDReset=T) THEN da ← 32 ELSE da ← 0;
IF (MnDFreeze=T) THEN da ← da + 16;
IF (MDExecute=T) THEN da ← da + 8;
IF (MDSerialIn=T) THEN da ← da + 4;
IF (MDAddress=T) THEN da ← da + 2;
IF (MDShiftCK=T) THEN da ← da + 1;
dregister ← da;
};
DBusWrite:
PROC []
RETURNS [] ~ {
Write[600FH,AssembleDbus[]]; -- Address of the DBus Register is "600FH"
};
DBusCheck:
PROC []
RETURNS [] ~ {
r : INT;
IF (MDSerialOut=T) THEN r ← dregister+128 ELSE r ← dregister;
ReadAndCheck[600FH,r];
};
SendDBusAddress:
PROC [address:
CARDINAL]
RETURNS [] ~ {
This Proc send an address on the DebugBus
adrs: CARDINAL ← address;
s: INT;
MDAddress ← T;
FOR s
IN [0..16)
DO
MDShiftCK ← F;
IF (BitOps.WShift[adrs,s-15] MOD 2) = 0 THEN MDSerialIn ← F
ELSE MDSerialIn ← T;
DBusWrite;
MDShiftCK ← T;
DBusWrite;
ENDLOOP;
MDAddress ← F;
MDShiftCK ← F;
DBusWrite;
};
SendDBusData:
PROC [value:
LONG
CARDINAL, count:
INT ← 16]
RETURNS [] ~ {
This proc send a data on the Debug Bus
FOR s:
INT
DECREASING IN [0..count)
DO
MDShiftCK ← F;
IF (BitOps.DShift[value,-s] MOD 2) = 0 THEN MDSerialIn ← F
ELSE MDSerialIn ← T;
DBusWrite;
MDShiftCK ← T;
DBusWrite;
ENDLOOP;
};
ReadDBusAndCheck:
PROC [value:
CARD, count:
INT ← 16]
RETURNS [] ~ {
Reading of a path with c transitions of ShiftCK
s: INT;
MDAddress ← F;
MDShiftCK ← F;
IF (BitOps.WShift[value,1-count] MOD 2) = 0 THEN MDSerialOut ← F
ELSE MDSerialOut ← T;
DBusWrite;
DBusCheck;
FOR s
IN [1..count)
DO
MDShiftCK ← T;
IF (BitOps.WShift[value,s-count+1] MOD 2) = 0 THEN MDSerialOut ← F
ELSE MDSerialOut ← T;
DBusWrite;
DBusCheck;
MDShiftCK ← F;
DBusWrite;
ENDLOOP;
};
SendShiftClock:
PROC []
RETURNS [] ~ {
This proc send 4 pulse of ShiftClock to allow the initialisation of DBus constant
FOR i:
NAT
IN [0..4)
DO
MDShiftCK ← T;
DBusWrite;
MDShiftCK ← F;
DBusWrite;
ENDLOOP;
};
SendReset:
PROC []
RETURNS [] ~ {
MnDReset ← F;
FOR lenghtReset: INT
IN [0..4)
DO
DBusWrite;
ENDLOOP;
MnDReset ← T;
DBusWrite;
};
AdDBus: PROC [bd,hyb,Int,ci,pth: CARDINAL 𡤀] RETURNS [ad: CARDINAL 𡤀] ~ {
Address in the DBus is :
<BoardNum:4><HybridNum:4><InterfaceNum:3><ChipNum:2><PathNum:3>
<ChipNum>=0 is for BIC
ad ← BitOps.WShift[bd,12]+BitOps.WShift[hyb,8];
ad ← ad+BitOps.WShift[Int,5]+BitOps.WShift[ci,3]+pth;
};
IdCte:
PROC [t,v:
CARDINAL]
RETURNS [id:
CARDINAL] ~ {
The structure of the Identificator is "0101 cccc ccrr rrrr"
cccccc is the Type, rrrrrr is the Version
id ← 5000H + BitOps.WShift[t,6] + v;
};
ResetOn: PROC [] RETURNS [] ~ {
This proc set reset
MnDReset ← F;
DBusWrite;
};
ResetOff: PROC [] RETURNS [] ~ {
This proc remove reset
MnDReset ← T;
DBusWrite;
};
Start of the Program
Here the program start :
Create or Append the file
outf ← FS.StreamOpen["FullBDDBus2.oracle", $create];
outf.PutF["-- Test D-Bus by PC interface\n"];
outf.PutF[" \n"];
outf.PutF["-- Output :\n"];
outf.PutF["-- Address: A, DataOut: B, nIOWPC: C, nIORPC: D \n"];
outf.PutF["-- Input :\n"];
outf.PutF["-- DataIn :M \n"];
outf.PutF[" \n"];
outf.PutF["-- A B C D ~ M \n"];
outf.PutF["\n"];
Start Generation :
lineCount← 0;
Init;
Send;
SendShiftClock; -- for autoload Dbus constant
ResetOn;
comment ← "Address of the MAP-Cache path Nb 4 for Stop Generation";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:1,ci:1,pth:4]]; -- "0000 0010 001 01 000"
comment ← "Stop Flip-Flop On";
SendDBusData[value:1,count:1];
ReadDBusAndCheck[value:1,count:1];
FOR sometime:
INT
IN [0..10)
DO --tempo
Send;
ENDLOOP;
ResetOff;
FOR sometime:
INT
IN [0..6)
DO --tempo
Send;
ENDLOOP;
comment ← "Stop Flip-Flop Off";
SendDBusData[value:0,count:1];
FOR lotofline:
INT
IN [0..200)
DO
Send;
ENDLOOP;
Board 1 controlled by Arbiter 1
Hybrid 0 contains only the Arbiter 1
comment ← "Address of the Arbiter 1 ID path";
SendDBusAddress[AdDBus[bd:1,hyb:0,Int:0,ci:0,pth:0]];
comment ← "ID of Display : type 1, version 1";
ReadDBusAndCheck[IdCte[t:1,v:1]];
Board 0 controlled by Arbiter 0
Hybrid 0 contains only the Arbiter 0
comment ← "Address of the Arbiter 0 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:0,Int:0,ci:0,pth:0]];
comment ← "ID of Display : type 1, version 1";
ReadDBusAndCheck[IdCte[t:1,v:1]];
Hybrid 1 contains 7 BICs
comment ← "Address of the BIC 0 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:0,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 8";
ReadDBusAndCheck[IdCte[t:2,v:8]];
comment ← "Address of the BIC 1 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:1,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 9";
ReadDBusAndCheck[IdCte[t:2,v:9]];
comment ← "Address of the BIC 2 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:2,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 10";
ReadDBusAndCheck[IdCte[t:2,v:10]];
comment ← "Address of the BIC 3 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:3,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 11";
ReadDBusAndCheck[IdCte[t:2,v:11]];
comment ← "Address of the BIC 4 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:4,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 12";
ReadDBusAndCheck[IdCte[t:2,v:12]];
comment ← "Address of the BIC 5 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:5,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 13";
ReadDBusAndCheck[IdCte[t:2,v:13]];
comment ← "Address of the BIC 6 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:1,Int:6,ci:0,pth:0]];
comment ← "ID of BIC type 2, Version 14";
ReadDBusAndCheck[IdCte[t:2,v:14]];
Hybrid 2 contains Display, MapCache, Cache IOB & 4 BICs
comment ← "Address of the Display ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:0,ci:1,pth:0]]; -- "0000 0010 000 01 000"
comment ← "ID of Display : type 8, version 1";
ReadDBusAndCheck[IdCte[t:8,v:1]]; -- "0101 001000 000001"
comment ← "Address of the Map-Cache ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:1,ci:1,pth:0]]; -- "0000 0010 001 01 000"
comment ← "ID of Map-Cache : type 9, version 1";
ReadDBusAndCheck[IdCte[t:9,v:1]]; -- "0101 001001 000001"
comment ← "Address of the Cache ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:2,ci:1,pth:0]]; -- "0000 0010 010 01 000"
comment ← "ID of Cache : type 5, version 1";
ReadDBusAndCheck[IdCte[t:5,v:1]]; -- "0101 000101 000001"
comment ← "Address of the IOB ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:3,ci:1,pth:0]]; -- "0000 0010 011 01 000"
comment ← "ID of IOB : type 7, version 1";
ReadDBusAndCheck[IdCte[t:7,v:1]]; -- "0101 000111 000001"
comment ← "Address of the BIC 0 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:0,ci:0,pth:0]]; -- "0000 0010 000 00 000"
comment ← "ID of BIC type 2, Version 0";
ReadDBusAndCheck[IdCte[t:2,v:0]]; -- "0101 000010 000000"
comment ← "Address of the BIC 1 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:1,ci:0,pth:0]]; -- "0000 0010 001 00 000"
comment ← "ID of BIC type 2, Version 1";
ReadDBusAndCheck[IdCte[t:2,v:1]]; -- "0101 000010 000001"
comment ← "Address of the BIC 2 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:2,ci:0,pth:0]]; -- "0000 0010 010 00 000"
comment ← "ID of BIC type 2, Version 2";
ReadDBusAndCheck[IdCte[t:2,v:2]]; -- "0101 000010 000010"
comment ← "Address of the BIC 3 ID path";
SendDBusAddress[AdDBus[bd:0,hyb:2,Int:3,ci:0,pth:0]]; -- "0000 0010 011 00 000"
comment ← "ID of BIC type 2, Version 3";
ReadDBusAndCheck[IdCte[t:2,v:3]]; -- "0101 000010 000011"
outf.PutF[". \n"]; -- end
outf.Close[];