<> <> <> <<>> <> <<>> DIRECTORY FS, IO, Rope, Convert, OracleGen, BitOps; GenFullBDDBus1Impl: CEDAR PROGRAM IMPORTS FS, IO, Rope, Convert, OracleGen, BitOps ~ BEGIN outf: IO.STREAM; lineCount : CARD; <> <<>> nr:INT = 1; --number of colums in the right side of the line nl:INT = 4; --number of colums in the left side of the line NbRight : TYPE = [0..nr); NbLeft : TYPE = [0..nl); RightLine: TYPE = ARRAY NbRight OF Rope.ROPE; LeftLine: TYPE = ARRAY NbLeft OF Rope.ROPE; rl: RightLine; ll: LeftLine; comment: Rope.ROPE; <> Signal : TYPE = {T,F,X}; MDSerialIn,MDExecute,MDAddress : Signal; MDShiftCK,MnDFreeze,MnDReset : Signal; MDSerialOut: Signal; IOWPC,IORPC,nIOWPC,nIORPC: Signal; Address, DataIn, DataOut, dregister : INT; --negative Data & Address means X Init: PROC [] RETURNS [] ~ { MDSerialIn _ X; MDExecute _ X; MDAddress _ X; MDShiftCK _ X; MnDFreeze _ T; MnDReset _ T; Address _ 0; DataIn _ -1; --negative INT means X DataOut _ -1; IOWPC _ F; IORPC _ F; MDSerialOut _ F; }; RopeFromSignal: PROC [s: Signal] RETURNS [r: Rope.ROPE] ~ { <> <<>> SELECT s FROM F => r _ "0"; T => r _ "1"; ENDCASE => r _ "X"; }; Inv: PROC [s: Signal] RETURNS [t: Signal] ~ { <> SELECT s FROM F => t _ T; T => t _ F; ENDCASE => t _ X; }; Send: PROC [] RETURNS [] ~ { <> <> <> <<>> <<>> <> nIOWPC _ Inv[IOWPC]; nIORPC _ Inv[IORPC]; IF Address >= 0 THEN ll[0] _ OracleGen.LExtend[OracleGen.Hex[Address],5] ELSE ll[0] _ "XXXXX"; IF DataOut >= 0 THEN ll[1] _ OracleGen.LExtend[OracleGen.Hex[DataOut],2] ELSE ll[1] _ "XX"; ll[1] _ Rope.Concat["XX",ll[1]]; ll[2] _ RopeFromSignal[nIOWPC]; ll[3] _ RopeFromSignal[nIORPC]; IF DataIn >= 0 THEN rl[0] _ OracleGen.LExtend[OracleGen.Hex[DataIn],2] ELSE rl[0] _ "XX"; rl[0] _ Rope.Concat["XX",rl[0]]; MergeOut; lineCount _ lineCount+ 1; }; MergeOut: PROC [] RETURNS [] ~ { <> <> <<>> column : INT; r : Rope.ROPE; r _ " "; FOR column IN [0..nl) DO r _ Rope.Cat[r,ll[column]," "]; ENDLOOP; r _ Rope.Cat[r," | "]; FOR column IN [0..nr) DO r _ Rope.Cat[r,rl[column]," "]; ENDLOOP; outf.PutF["%g -- %g %g \n",IO.rope[r],IO.rope[Convert.RopeFromInt[lineCount]],IO.rope[comment]]; comment _ "" }; Write: PROC [adrs : INT,da : INT] RETURNS [] ~ { Address _ adrs; DataOut _ da; Send; IOWPC _ T; Send; IOWPC _ F; Send; comment _ " Write Data out"; DataOut _ -1; Send; }; ReadAndCheck: PROC [adrs : INT,da : INT] RETURNS [] ~ { Address _ adrs; Send; IORPC _ T; Send; comment _ " ReadAndCheck Data"; DataIn _ da; Send; IORPC _ F; DataIn _ -1; Send; }; AssembleDbus: PROC [] RETURNS [da: INT] ~ { IF (MnDReset=T) THEN da _ 32 ELSE da _ 0; IF (MnDFreeze=T) THEN da _ da + 16; IF (MDExecute=T) THEN da _ da + 8; IF (MDSerialIn=T) THEN da _ da + 4; IF (MDAddress=T) THEN da _ da + 2; IF (MDShiftCK=T) THEN da _ da + 1; dregister _ da; }; DBusWrite: PROC [] RETURNS [] ~ { Write[600FH,AssembleDbus[]]; -- Address of the DBus Register is "600FH" }; DBusCheck: PROC [] RETURNS [] ~ { r : INT; IF (MDSerialOut=T) THEN r _ dregister+128 ELSE r _ dregister; ReadAndCheck[600FH,r]; }; SendDBusAddress: PROC [address: CARDINAL] RETURNS [] ~ { <> adrs: CARDINAL _ address; s: INT; MDAddress _ T; FOR s IN [0..16) DO MDShiftCK _ F; IF (BitOps.WShift[adrs,s-15] MOD 2) = 0 THEN MDSerialIn _ F ELSE MDSerialIn _ T; DBusWrite; MDShiftCK _ T; DBusWrite; ENDLOOP; MDAddress _ F; MDShiftCK _ F; DBusWrite; }; ReadDBusAndCheck: PROC [v: CARD, c: INT _ 16] RETURNS [] ~ { <> <<>> s: INT; value: CARD _ v; MDAddress _ F; MDShiftCK _ F; IF (BitOps.WShift[value,1-c] MOD 2) = 0 THEN MDSerialOut _ F ELSE MDSerialOut _ T; DBusWrite; DBusCheck; FOR s IN [1..c) DO MDShiftCK _ T; IF (BitOps.WShift[value,s-c+1] MOD 2) = 0 THEN MDSerialOut _ F ELSE MDSerialOut _ T; DBusWrite; DBusCheck; MDShiftCK _ F; DBusWrite; ENDLOOP; }; AdDBus: PROC [bd,hyb,Int,ci,pth: CARDINAL _0] RETURNS [ad: CARDINAL _0] ~ { <

> <<>> << =0 is for BIC>> <<>> ad _ BitOps.WShift[bd,12]+BitOps.WShift[hyb,8]; ad _ ad+BitOps.WShift[Int,5]+BitOps.WShift[ci,3]+pth; }; IdCte: PROC [t,v:CARDINAL] RETURNS [id:CARDINAL] ~ { <> <> <<>> id _ 5000H + BitOps.WShift[t,6] + v; }; <> <> <> <<>> outf _ FS.StreamOpen["FullBDDBus1.oracle", $create]; outf.PutF["-- Test D-Bus by PC interface\n"]; outf.PutF[" \n"]; outf.PutF["-- Output :\n"]; outf.PutF["-- Address: A, DataOut: B, nIOWPC: C, nIORPC: D \n"]; outf.PutF["-- Input :\n"]; outf.PutF["-- DataIn :M \n"]; outf.PutF[" \n"]; outf.PutF["-- A B C D ~ M \n"]; outf.PutF["\n"]; <> <<>> lineCount_ 0; Init; Send; <> <<>> << Hybrid 0 contains only the Arbiter 1>> <<>> comment _ "Address of the Arbiter 1 ID path"; SendDBusAddress[AdDBus[bd:1,hyb:0,Int:0,ci:0,pth:0]]; comment _ "ID of Display : type 1, version 1"; ReadDBusAndCheck[IdCte[t:1,v:1]]; <<>> <> <<>> << Hybrid 0 contains only the Arbiter 0>> <<>> comment _ "Address of the Arbiter 0 ID path"; SendDBusAddress[AdDBus[bd:0,hyb:0,Int:0,ci:0,pth:0]]; comment _ "ID of Display : type 1, version 1"; ReadDBusAndCheck[IdCte[t:1,v:1]]; <<>> <<>> << Hybrid 1 contains 7 BICs>> <<>> comment _ "Address of the BIC 0 ID path"; SendDBusAddress[AdDBus[bd:0,hyb:1,Int:0,ci:0,pth:0]]; comment _ "ID of BIC type 2, Version 8"; ReadDBusAndCheck[IdCte[t:2,v:8]]; comment _ "Address of the BIC 1 ID path"; SendDBusAddress[AdDBus[bd:0,hyb:1,Int:1,ci:0,pth:0]]; comment _ "ID of BIC type 2, Version 9"; ReadDBusAndCheck[IdCte[t:2,v:9]]; <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <<>> << Hybrid 2 contains Display, MapCache, Cache IOB & 4 BICs>> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <> <> <> <> <<>> <<>> <<>> <<>> outf.PutF[". \n"]; -- end outf.Close[]; END.