DIRECTORY
BitOps, Core, DynaBusInterface, FSM, IO, SmallCacheLogic, SymTab;

SmallCachePmCodeFSM: CEDAR PROGRAM
IMPORTS BitOps, FSM, SymTab
EXPORTS SmallCacheLogic
~ BEGIN
microStateIndex:	INT _ 1;
microStates:		SymTab.Ref _ SymTab.Create[];
RegisterState: PROC[state: IO.ROPE] RETURNS[IO.ROPE] = {
[]_SymTab.Store[microStates, state, NEW[INT _ microStateIndex]];
microStateIndex _ microStateIndex+1;
RETURN[state]};
StateIndex:	PUBLIC PROC[state: IO.ROPE] RETURNS[index: INT _ -1] = {
IF ~SymTab.Fetch[microStates, state].found THEN ERROR;
RETURN[ NARROW[SymTab.Fetch[microStates, state].val, REF INT]^]};
StateName:	PUBLIC PROC[index: INT]	RETURNS[state: IO.ROPE _ NIL] = {
action: SymTab.EachPairAction = {
IF index = NARROW[val, REF INT]^ THEN {state _ key; RETURN[TRUE]}};
IF NOT SymTab.Pairs[microStates, action] THEN ERROR};

Init:								IO.ROPE _ RegisterState["Init"];

ChkPermPC:					IO.ROPE _ RegisterState["ChkPermPC"];
CP1PC:								IO.ROPE _ RegisterState["CP1PC"];
CP2PC:								IO.ROPE _ RegisterState["CP2PC"];
CP3PC:								IO.ROPE _ RegisterState["CP3PC"];
HandleMissPC:				IO.ROPE _ RegisterState["HandleMissPC"];
HM1PC:							IO.ROPE _ RegisterState["HM1PC"];
HM2PC:							IO.ROPE _ RegisterState["HM2PC"];
HM3PPC:							IO.ROPE _ RegisterState["HM3PPC"];
HM3nPPC:						IO.ROPE _ RegisterState["HM3nPPC"];
HM3nRPC:						IO.ROPE _ RegisterState["HM3nRPC"];
HMnMPC:						IO.ROPE _ RegisterState["HMnMPC"];
HMnM11PC:					IO.ROPE _ RegisterState["HMnM11PC"];
HMnM12PC:					IO.ROPE _ RegisterState["HMnM12PC"];
HMnM2PC:						IO.ROPE _ RegisterState["HMnM2PC"];
HMnM3PC:						IO.ROPE _ RegisterState["HMnM3PC"];
HMnM4PC:						IO.ROPE _ RegisterState["HMnM4PC"];
HMRCamReadyPC:			IO.ROPE _ RegisterState["HMRCamReadyPC"];
HMReadRamPC:				IO.ROPE _ RegisterState["HMReadRamPC"];
HMReturn1PC:					IO.ROPE _ RegisterState["HMReturn1PC"];
HMReturn2PC:					IO.ROPE _ RegisterState["HMReturn2PC"];
HMReturn3PC:					IO.ROPE _ RegisterState["HMReturn3PC"];
HMReturn4PC:					IO.ROPE _ RegisterState["HMReturn4PC"];
HMReturn5PC:					IO.ROPE _ RegisterState["HMReturn5PC"];
HMRR2PC:						IO.ROPE _ RegisterState["HMRR2PC"];
HMRR3PC:						IO.ROPE _ RegisterState["HMRR3PC"];
HMRR4PC:						IO.ROPE _ RegisterState["HMRR4PC"];
HMRRCVct2PC:				IO.ROPE _ RegisterState["HMRRCVct2PC"];
HMRRCVct3PC:				IO.ROPE _ RegisterState["HMRRCVct3PC"];
HMRRCVct4PC:				IO.ROPE _ RegisterState["HMRRCVct4PC"];
HMRRCVM3PC:					IO.ROPE _ RegisterState["HMRRCVM3PC"];
HMRRCVM4PC:					IO.ROPE _ RegisterState["HMRRCVM4PC"];
IdlePC:							IO.ROPE _ RegisterState["IdlePC"];
IOR2PC:							IO.ROPE _ RegisterState["IOR2PC"];
IOWritePC:						IO.ROPE _ RegisterState["IOWritePC"];
PCWS3PC:							IO.ROPE _ RegisterState["PCWS3PC"];
PCWS4PC:							IO.ROPE _ RegisterState["PCWS4PC"];
PCWS5PC:							IO.ROPE _ RegisterState["PCWS5PC"];
PCWS6PC:							IO.ROPE _ RegisterState["PCWS6PC"];
PCWS7PC:							IO.ROPE _ RegisterState["PCWS7PC"];
PCWS8PC:							IO.ROPE _ RegisterState["PCWS8PC"];
PCWS9PC:							IO.ROPE _ RegisterState["PCWS9PC"];
PCWS10PC:							IO.ROPE _ RegisterState["PCWS10PC"];
PCWS11PC:							IO.ROPE _ RegisterState["PCWS11PC"];
PCWS12PC:							IO.ROPE _ RegisterState["PCWS12PC"];
PCWS13PC:							IO.ROPE _ RegisterState["PCWS13PC"];
PCWS14PC:							IO.ROPE _ RegisterState["PCWS14PC"];
PCWS14PrimePC:				IO.ROPE _ RegisterState["PCWS14PrimePC"];
PCWS15PC:							IO.ROPE _ RegisterState["PCWS15PC"];
PCWS16PC:							IO.ROPE _ RegisterState["PCWS16PC"];
PCWS17PC:							IO.ROPE _ RegisterState["PCWS17PC"];
PCWSR2PC:						IO.ROPE _ RegisterState["PCWSR2PC"];
PCWSRetryPC:					IO.ROPE _ RegisterState["PCWSRetryPC"];
PSR2PC:							IO.ROPE _ RegisterState["PSR2PC"];
PSR2PrimePC:					IO.ROPE _ RegisterState["PSR2PrimePC"];
PSR3PC:							IO.ROPE _ RegisterState["PSR3PC"];
PSR4PC:							IO.ROPE _ RegisterState["PSR4PC"];
PSRetryPC:						IO.ROPE _ RegisterState["PSRetryPC"];
PSRetryPrimePC:				IO.ROPE _ RegisterState["PSRetryPrimePC"];
PSReturn1PC:					IO.ROPE _ RegisterState["PSReturn1PC"];
PSReturn2PC:					IO.ROPE _ RegisterState["PSReturn2PC"];
PSRCamReadyPC:				IO.ROPE _ RegisterState["PSRCamReadyPC"];
PSRRCVM2PC:						IO.ROPE _ RegisterState["PSRRCVM2PC"];
PSRRCVM3PC:						IO.ROPE _ RegisterState["PSRRCVM3PC"];
PSRRCVM4PC:						IO.ROPE _ RegisterState["PSRRCVM4PC"];
PStorePC:						IO.ROPE _ RegisterState["PStorePC"];
SBTOF2PC:						IO.ROPE _ RegisterState["SBTOF2PC"];
SBTOF3PC:						IO.ROPE _ RegisterState["SBTOF3PC"];
SIOAF2PC:							IO.ROPE _ RegisterState["SIOAF2PC"];
SIOAF3PC:							IO.ROPE _ RegisterState["SIOAF3PC"];
SMAF2PC:							IO.ROPE _ RegisterState["SMAF2PC"];
SMAF3PC:							IO.ROPE _ RegisterState["SMAF3PC"];
StoreBTimeOutFaultPC:		IO.ROPE _ RegisterState["StoreBTimeOutFaultPC"];
StoreMemAccessFaultPC:	IO.ROPE _ RegisterState["StoreMemAccessFaultPC"];
StoreIOAccessFaultPC:		IO.ROPE _ RegisterState["StoreIOAccessFaultPC"];
TestReadRamPC:				IO.ROPE _ RegisterState["TestReadRamPC"];
TestReadRCamPC:				IO.ROPE _ RegisterState["TestReadRCamPC"];
TestReadVCamPC:			IO.ROPE _ RegisterState["TestReadVCamPC"];
TestResetVictimPC:			IO.ROPE _ RegisterState["TestResetVictimPC"];
TestShiftVictimPC:			IO.ROPE _ RegisterState["TestShiftVictimPC"];
TRR2PC:							IO.ROPE _ RegisterState["TRR2PC"];
TRR3PC:							IO.ROPE _ RegisterState["TRR3PC"];
TRV2PC:							IO.ROPE _ RegisterState["TRV2PC"];
TRRC2PC:							IO.ROPE _ RegisterState["TRRC2PC"];
TRRC3PC:							IO.ROPE _ RegisterState["TRRC3PC"];
TRRC4PC:							IO.ROPE _ RegisterState["TRRC4PC"];
TRRC5PC:							IO.ROPE _ RegisterState["TRRC5PC"];
TRRC6PC:							IO.ROPE _ RegisterState["TRRC6PC"];
TRVC2PC:							IO.ROPE _ RegisterState["TRVC2PC"];
TRVC3PC:							IO.ROPE _ RegisterState["TRVC3PC"];
TRVC4PC:							IO.ROPE _ RegisterState["TRVC4PC"];
TRVC5PC:							IO.ROPE _ RegisterState["TRVC5PC"];
TRVC6PC:							IO.ROPE _ RegisterState["TRVC6PC"];
TSV2PC:							IO.ROPE _ RegisterState["TSV2PC"];
TSV3PC:							IO.ROPE _ RegisterState["TSV3PC"];

NumPCBits:		PUBLIC NAT	_ BitOps.NBits[microStateIndex];
NumStackBits:	PUBLIC NAT	_ 2;


SmallCachePmCode: PUBLIC PROC
[usePC: BOOL _ TRUE, reg: FSM.RegisterType _ none, impl: ATOM _ $PLA]
RETURNS [ct: Core.CellType] = {
machName:		IO.ROPE			_ "SmallCachePmCode";
fsm:				FSM.FSMData	_ NIL;
ctx:			FSM.Context _ FSM.Create[machName];
IfState:		PROC[s: IO.ROPE]							= {FSM.IfState		[ctx,s]};
If:				PROC[f, v: NAT, m: NAT _ FSM.default]	= {FSM.If				[ctx,f,v,m]};
And:			PROC[f, v: NAT, m: NAT _ FSM.default]	= {FSM.And			[ctx,f,v,m]};
AddOut:		PROC[f, v: NAT, m: NAT _ FSM.default]	= {FSM.AddOut		[ctx,f,v,m]};
EndIf:		PROC											= {FSM.JmpState		[ctx, NIL]};
T:									NAT = 1;
F:									NAT = 0;
NumPCmdBits:					NAT = 4;
FromRead,
FromIORead:					NAT = 0;
FromWrite,
FromIOWrite:					NAT = 1;
FromCWS:						NAT = 2; -- FromCWS encoded as 2 or 3 in HMReturn2PC

ABusPAdd:						NAT = 0;
ABusRqstBuf:					NAT = 1;
ABusVCam:					NAT = 4;
ABusCam:						NAT = 6;
ABusRCam:						NAT = 7;
ABusIOOld:					NAT = 8;
ABusIONew:					NAT = 9;
ABusIOAId:					NAT = 12;
ABusIOFault:					NAT = 13;
ABusFault:						NAT = 8;
DBusNoOp:						NAT = 0;
DBusPWtLatch:				NAT = 1;
DBusRRLatch:					NAT = 2;
DBusABus:						NAT = 3;
SCmdNoOp:						NAT = 0;
SCmdLRM:						NAT = 1;
SCmdLVM:						NAT = 2;
SCmdVictim:					NAT = 3;
PCmdNoOp:						NAT = 7;
PCmdRead:						NAT = 8;
PCmdWrite:						NAT = 9;
PCmdCWS:						NAT = 10;
PCmdDeMap:					NAT = 11;
PCmdIORead:					NAT = 12;
PCmdIOWrite:					NAT = 13;
PCmd14:							NAT = 14; -- used only as mask for PCmdBIOWrite
PCmdBIOWrite:				NAT = 15; -- encoded as 14 or 15 using PCmd14 - djc
BCmdBIOW:					NAT = ORD[DynaBusInterface.Cmd.BIOWRqst]/2;
BCmdCWS:						NAT = ORD[DynaBusInterface.Cmd.CWSRqst]/2;
BCmdDeMap:					NAT = ORD[DynaBusInterface.Cmd.DeMapRqst]/2;
BCmdFB:						NAT = ORD[DynaBusInterface.Cmd.FBRqst]/2;
BCmdIOR:						NAT = ORD[DynaBusInterface.Cmd.IORRqst]/2;
BCmdIOW:						NAT = ORD[DynaBusInterface.Cmd.IOWRqst]/2;
BCmdMap:						NAT = ORD[DynaBusInterface.Cmd.MapRqst]/2;
BCmdRB:						NAT = ORD[DynaBusInterface.Cmd.RBRqst]/2;
BCmdWB:						NAT = ORD[DynaBusInterface.Cmd.WBRqst]/2;
BCmdWS:						NAT = ORD[DynaBusInterface.Cmd.WSRqst]/2;
FaultMemAccess:				NAT = 0;
FaultIOAccess:				NAT = 1;
FaultBTimeOut:				NAT = 2;
ASh:							NAT = ctx.Declare["ASh",					in];
AVM:							NAT = ctx.Declare["AVM",					in];
FBTIP:							NAT = ctx.Declare["FBTIP ",				in];
MyBFault:					NAT = ctx.Declare["MyBFault",			in];
NonFBTIP:					NAT = ctx.Declare["NonFBTIP",			in];
PAccessPerm:				NAT = ctx.Declare["PAccessPerm",			in];
PCmd:						NAT = ctx.Declare["PCmd",					in,	NumPCmdBits];
PCWSEq:					NAT = ctx.Declare["PCWSEq",				in];
RamForP:					NAT = ctx.Declare["RamForP",				in];
RCamForP:					NAT = ctx.Declare["RCamForP",			in];
RPValid:					NAT = ctx.Declare["RPValid",				in];
TestCode:					NAT = ctx.Declare["TestCode",				in,	3];
TimeOut:					NAT = ctx.Declare["TimeOut",				in];
TopOfStack:				NAT = ctx.Declare["TopOfStack",			in,	NumStackBits];
Reset:						NAT = ctx.Declare["Reset",					in];
PC:		NAT _ IF usePC THEN ctx.Declare["PC", outIn,	NumPCBits] ELSE 0;

PCtlABusCmd:				NAT = ctx.Declare["PCtlABusCmd",			out,	4];
PCtlBCmd:					NAT = ctx.Declare["PCtlBCmd",				out,	4];	-- Xs
PCtlIdle:						NAT = ctx.Declare["PCtlIdle",					out];
PCtlCSCmd:					NAT = ctx.Declare["PCtlCSCmd",				out,	2];
PCtlDBusCmd:				NAT = ctx.Declare["PCtlDBusCmd",			out,	2];
PCtlEnCamSel:				NAT = ctx.Declare["PCtlEnCamSel",			out];
PCtlEnCamSelExt:			NAT = ctx.Declare["PCtlEnCamSelExt",		out];
PCtlFault:					NAT = ctx.Declare["PCtlFault",					out];
PCtlFaultCode:			NAT = ctx.Declare["PCtlFaultCode",			out,	2];
PCtlForceWordAddress:	NAT = ctx.Declare["PCtlForceWordAddress",	out];
PCtlPartFMch:				NAT = ctx.Declare["PCtlPartFMch",			out];
PCtlFrzVictim:			NAT = ctx.Declare["PCtlFrzVictim",			out];
PCtlLdFIFOSetFBTIP:	NAT = ctx.Declare["PCtlLdFIFOSetFBTIP",	out];
PCtlLdFlagsReg:			NAT = ctx.Declare["PCtlLdFlagsReg",			out];
PCtlLdRBufDataLo:		NAT = ctx.Declare["PCtlLdRBufDataLo",		out];
PCtlLdRBufDataHi:		NAT = ctx.Declare["PCtlLdRBufDataHi",		out];
PCtlLdRBufHeader:		NAT = ctx.Declare["PCtlLdRBufHeader",		out];
PCtlLdSnooperSetValid:	NAT = ctx.Declare["PCtlLdSnooperSetValid",	out];
PCtlPartVMch:			NAT = ctx.Declare["PCtlPartVMch",			out];
PCtlRdRam:					NAT = ctx.Declare["PCtlRdRam",				out];
PCtlRdRCam:				NAT = ctx.Declare["PCtlRdRCam",				out];
PCtlRdVCam:				NAT = ctx.Declare["PCtlRdVCam",				out];
PCtlReleaseP:				NAT = ctx.Declare["PCtlReleaseP",				out];
PCtlResetVictim:			NAT = ctx.Declare["PCtlResetVictim",			out];
PCtlRSCmd:					NAT = ctx.Declare["PCtlRSCmd",				out,	2];
PCtlSelBFC:				NAT = ctx.Declare["PCtlSelBFC",				out];
PCtlSelRplyData:			NAT = ctx.Declare["PCtlSelRplyData",			out];
PCtlSetNonFBTIP:			NAT = ctx.Declare["PCtlSetNonFBTIP",		out];
PCtlShftVictim:			NAT = ctx.Declare["PCtlShftVictim",			out];
PCtlWtMchVCam:			NAT = ctx.Declare["PCtlWtMchVCam",		out];
PCtlWtRam:					NAT = ctx.Declare["PCtlWtRam",				out];
Push:							NAT = ctx.Declare["Push",						out];
Stack:						NAT = ctx.Declare["Stack",				out,	NumStackBits]; -- Xs
ReadRCam1: PROC [] = {
AddOut[PCtlRdRCam,		T];
AddOut[PCtlEnCamSel,		T];
AddOut[PCtlEnCamSelExt,	F]};

ReadRCam2: PROC [sCmd: NAT] = {
AddOut[PCtlRdRCam,		T];
AddOut[PCtlEnCamSel,		T];
AddOut[PCtlEnCamSelExt,	F];
AddOut[PCtlCSCmd,	sCmd] };

ReadRCam34: PROC [sCmd: NAT] = {
AddOut[PCtlCSCmd,			sCmd] };

ReadVCam1: PROC [sCmd: NAT] = {
AddOut[PCtlRdVCam,		T];
AddOut[PCtlEnCamSel,		T];
AddOut[PCtlEnCamSelExt,	F]};

ReadVCam2: PROC [sCmd: NAT] = {
AddOut[PCtlRdVCam,		T];
AddOut[PCtlEnCamSel,		T];
AddOut[PCtlEnCamSelExt,	F];
AddOut[PCtlCSCmd,		sCmd]};

ReadVCam34: PROC [sCmd: NAT] = {
AddOut[PCtlCSCmd,	sCmd]};

ReadRam1: PROC [sCmd: NAT, drDBus: {DBus, NoDBus} _ DBus] = {
AddOut[PCtlRSCmd,	sCmd];
AddOut[PCtlRdRam,	T]};

ReadRam2: PROC [sCmd: NAT, drDBus: {DBus, NoDBus} _ DBus] = {
IF drDBus = DBus THEN AddOut[PCtlDBusCmd, DBusRRLatch]};

ReadRam3: PROC [sCmd: NAT, drDBus: {DBus, NoDBus} _ DBus] = {
IF drDBus = DBus THEN AddOut[PCtlDBusCmd, DBusRRLatch]};

WriteRam1: PROC [sCmd: NAT, data: NAT] = {
AddOut[PCtlRSCmd,	sCmd];
AddOut[PCtlWtRam,	T]};

WriteRam2: PROC [sCmd: NAT, data: NAT] = {
AddOut[PCtlRSCmd,	sCmd];
AddOut[PCtlDBusCmd,	data]};

WriteRam3: PROC [sCmd: NAT, data: NAT] = {
AddOut[PCtlDBusCmd,	data]};

JmpState: PROC [dest: IO.ROPE] = {
SELECT dest FROM
StoreBTimeOutFaultPC,
StoreMemAccessFaultPC,
StoreIOAccessFaultPC	=> {
AddOut[PCtlABusCmd,			ABusIOFault];
AddOut[PCtlWtMchVCam,		T]};
IdlePC	=> {
AddOut[PCtlIdle,				T];
AddOut[PCtlLdRBufDataLo,	T]};
ENDCASE;
IF usePC THEN AddOut[PC, StateIndex[dest]];
FSM.JmpState[ctx, dest]};
IfState[NIL];
AddOut[Push,		T];
AddOut[Stack,	FromRead];
JmpState[Init];

IfState[Init];	-- Test dispatching - djc
If[f: TestCode, v: 0, m: 6];	JmpState[IdlePC];				-- 0, 1
If[f: TestCode, v: 2, m: 6];	JmpState[TestReadRamPC];		-- 2, 3
If[f: TestCode, v: 4];		JmpState[TestReadRCamPC];	-- 4
If[f: TestCode, v: 5];		JmpState[TestReadVCamPC];	-- 5
If[f: TestCode, v: 6];		JmpState[TestShiftVictimPC];	-- 6
If[f: TestCode, v: 7];		JmpState[TestResetVictimPC];	-- 7
EndIf[];

IfState[IdlePC];
If[f: PCmd, v: 0, m: PCmdRead];	-- TRUE if less THAN PCmdRead=8
JmpState[IdlePC];

If[PCmd, PCmdRead];
If[AVM, T];
JmpState[HandleMissPC];
If[AVM, F];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack,	FromRead];
JmpState[HandleMissPC ];
EndIf[];

If[PCmd, PCmdWrite];
If[AVM, T];
JmpState[PStorePC];
If[AVM, F];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack,	FromWrite];
JmpState[HandleMissPC ];
EndIf[];

If[PCmd, PCmdCWS];
If[AVM, T];
AddOut[PCtlABusCmd,	ABusIOOld];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS3PC];
If[AVM, F];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack,	FromCWS];
JmpState[HandleMissPC ];
EndIf[];

If[PCmd, PCmdIORead];
If[AVM, T];
JmpState[IdlePC];
If[AVM, F];
AddOut[PCtlPartFMch ,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack, FromIORead];
JmpState[ChkPermPC];
EndIf[];

If[PCmd, PCmdIOWrite];
If[AVM, T];
JmpState[IdlePC];
If[AVM, F];
AddOut[PCtlPartFMch ,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack, FromIOWrite];
JmpState[ChkPermPC];
EndIf[];

If[PCmd, PCmdBIOWrite, PCmd14];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlSetNonFBTIP,	T];
AddOut[PCtlBCmd, BCmdBIOW];
AddOut[PCtlABusCmd, ABusPAdd];
JmpState[PSReturn1PC];

If[PCmd, PCmdDeMap];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlSetNonFBTIP,	T];
AddOut[PCtlBCmd, BCmdDeMap];
AddOut[PCtlABusCmd, ABusPAdd];
JmpState[PSReturn1PC];
EndIf[];

IfState[ChkPermPC];
JmpState[CP1PC];

IfState[CP1PC];
JmpState[CP2PC];

IfState[CP2PC];
JmpState[CP3PC];

IfState[CP3PC];
If[AVM, T];
JmpState[StoreIOAccessFaultPC];

If[AVM, F];
AddOut[PCtlABusCmd,	ABusPAdd];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlDBusCmd,	DBusPWtLatch];
AddOut[PCtlLdRBufDataLo,	T];
AddOut[PCtlLdRBufDataHi,	T];
AddOut[PCtlSetNonFBTIP,	T];
If[TopOfStack, FromIOWrite, 1]; -- assume only FromIORead, FromIOWrite possible - djc
AddOut[PCtlBCmd,	BCmdIOW];
JmpState[PSReturn1PC];
If[TopOfStack, FromIORead, 1]; -- assume only FromIORead, FromIOWrite possible - djc
AddOut[PCtlBCmd,	BCmdIOR];
JmpState[PSReturn1PC];
EndIf[];
EndIf[];

IfState[IOR2PC];
If[NonFBTIP, T];	And[TimeOut, F];
JmpState[IOR2PC];

If[NonFBTIP, T];	And[TimeOut, T];
JmpState[StoreBTimeOutFaultPC];

If[NonFBTIP, F];	And[MyBFault, T];
AddOut[PCtlFault,	T];
AddOut[PCtlSelBFC,	T];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];

If[NonFBTIP, F];	And[MyBFault, F];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];
EndIf[];

IfState[PCWSRetryPC];
JmpState[PCWSR2PC];

IfState[PCWSR2PC];
AddOut[PCtlABusCmd,	ABusIOOld];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS3PC];

IfState[PCWS3PC];
ReadRam1[SCmdLVM];
JmpState[PCWS4PC];

IfState[PCWS4PC];
If[AVM, T];
ReadRam2[SCmdLVM];
JmpState[PCWS5PC];
If[AVM, F];
ReadRam2[SCmdLVM];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack,	FromCWS];
JmpState[HandleMissPC];
EndIf[];

IfState[PCWS5PC];
If[RamForP, T];
AddOut[PCtlLdRBufDataHi,	T];
ReadRam3[SCmdLVM];
JmpState[PCWS6PC];

If[RamForP, F];
ReadRam1[SCmdLVM];
JmpState[PCWS4PC];
EndIf[];

IfState[PCWS6PC];
JmpState[PCWS7PC];

IfState[PCWS7PC];
If[PCWSEq, T];
AddOut[PCtlABusCmd, ABusIONew];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS8PC];

If[PCWSEq, F];
JmpState[IdlePC];
EndIf[];

IfState[PCWS8PC];
ReadRam1[SCmdLVM];
JmpState[PCWS9PC];

IfState[PCWS9PC];
ReadRam2[SCmdLVM];
AddOut[PCtlABusCmd, ABusPAdd];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS10PC];

IfState[PCWS10PC];
If[RamForP, T];
ReadRam3[SCmdLVM];
WriteRam1[SCmdLVM, DBusRRLatch];
JmpState[PCWS11PC];

If[RamForP, F];
AddOut[PCtlABusCmd, ABusIONew];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS8PC];
EndIf[];

IfState[PCWS11PC];
WriteRam2[SCmdLVM, DBusRRLatch];
JmpState[PCWS12PC];

IfState[PCWS12PC];
If[RamForP, T];
WriteRam3[SCmdLVM, DBusRRLatch];
AddOut[PCtlWtMchVCam,	T];
AddOut[PCtlABusCmd, ABusPAdd];
JmpState[PCWS13PC];

If[RamForP, F];
AddOut[PCtlABusCmd, ABusIONew];
AddOut[PCtlWtMchVCam,	T];
JmpState[PCWS8PC];
EndIf[];

IfState[PCWS13PC];
ReadRCam1[];
JmpState[PCWS14PC];

IfState[PCWS14PC];
If[ASh, T];	And[RCamForP, T];
ReadRCam2[SCmdLVM];
JmpState[PCWS15PC];

If[ASh, T];	And[RCamForP, F];
ReadRCam1[];
JmpState[PCWS14PrimePC];

If[ASh, F];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];
EndIf[];

IfState[PCWS14PrimePC];
If[RCamForP, T];
ReadRCam2[SCmdLVM];
JmpState[PCWS15PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PCWS14PrimePC];
EndIf[];

IfState[PCWS15PC];
If[RCamForP, T];
ReadRCam34[SCmdLVM];
JmpState[PCWS16PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PCWS14PrimePC];
EndIf[];

IfState[PCWS16PC];
If[RCamForP, T];
AddOut[PCtlSetNonFBTIP,	T];
ReadRCam34[SCmdLVM];
JmpState[PCWS17PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PCWS14PrimePC];
EndIf[];

IfState[PCWS17PC];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlBCmd, BCmdCWS];
AddOut[PCtlABusCmd, ABusCam];
JmpState[PSReturn2PC];

IfState[PSRetryPC];
WriteRam1[SCmdLVM, DBusPWtLatch];
JmpState[PSR2PC];

IfState[PSR2PrimePC];
If[AVM, T];
WriteRam2[SCmdLVM, DBusPWtLatch];
JmpState[PSR3PC];

If[AVM, F];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack, FromWrite];
JmpState[HandleMissPC];
EndIf[];

IfState[PSR2PC];
WriteRam2[SCmdLVM, DBusPWtLatch];
JmpState[PSR3PC];

IfState[PSR3PC];
If[RamForP, T];
WriteRam3[SCmdLVM, DBusPWtLatch];
JmpState[PSR4PC];

If[RamForP, F];
WriteRam1[SCmdLVM, DBusPWtLatch];
JmpState[PSR2PrimePC];
EndIf[];

IfState[PSR4PC];
If[AVM, T];
JmpState[PStorePC];

If[AVM, F];
AddOut[PCtlPartVMch,	T];
AddOut[PCtlWtMchVCam,	T];
AddOut[Push,	T];
AddOut[Stack, FromWrite];
JmpState[HandleMissPC];
EndIf[];

IfState[PStorePC];
If[ASh, T];
ReadRCam1[];
JmpState[PSRRCVM2PC];

If[ASh, F];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];
EndIf[];

IfState[PSRRCVM2PC];
If[RCamForP, T];
ReadRCam2[SCmdLVM];
JmpState[PSRRCVM3PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PSRRCVM2PC];
EndIf[];

IfState[PSRRCVM3PC];
If[RCamForP, T];
ReadRCam34[SCmdLVM];
JmpState[PSRRCVM4PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PSRRCVM2PC];
EndIf[];

IfState[PSRRCVM4PC];
If[RCamForP, T];
AddOut[PCtlSetNonFBTIP,	T];
ReadRCam34[SCmdLVM];
JmpState[PSRCamReadyPC];

If[RCamForP, F];
ReadRCam1[];
JmpState[PSRRCVM2PC];
EndIf[];

IfState[PSRCamReadyPC];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlBCmd, BCmdWS];
AddOut[PCtlABusCmd, ABusCam];
JmpState[PSReturn2PC];

IfState[PSReturn1PC];
JmpState[PSReturn2PC];

IfState[PSReturn2PC];
If[NonFBTIP, T];	And[TimeOut, F];
AddOut[PCtlSelRplyData,	T];
JmpState[PSReturn2PC];

If[NonFBTIP, T];	And[TimeOut, T];
AddOut[PCtlSelRplyData,	T];
JmpState[StoreBTimeOutFaultPC];

If[NonFBTIP, F];	And[MyBFault, T];
AddOut[PCtlFault,	T];
AddOut[PCtlSelBFC,	T];
AddOut[PCtlReleaseP,	T];
AddOut[PCtlSelRplyData,	T];
JmpState[IdlePC];

If[NonFBTIP, F];	And[MyBFault, F];
AddOut[PCtlReleaseP,	T];
AddOut[PCtlSelRplyData,	T];
JmpState[IdlePC];
EndIf[];

IfState[HandleMissPC];
AddOut[PCtlFrzVictim,	T];
JmpState[HM1PC];

IfState[HM1PC];
ReadRCam1[];
AddOut[PCtlFrzVictim,	T];
JmpState[HM2PC];

IfState[HM2PC];
If[RCamForP, T];
ReadRCam2[SCmdLVM];
JmpState[HM3PPC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HM3nPPC];
EndIf[];

IfState[HM3PPC];
If[AVM, T];	And[RCamForP, T];
ReadRCam34[SCmdLVM];
JmpState[HMRRCVM4PC];

If[AVM, T];	And[RCamForP, F];
ReadRCam1[];
JmpState[HM3nPPC];

If[AVM, F];
AddOut[PCtlABusCmd, ABusIOAId];
AddOut[PCtlWtMchVCam,	T];
JmpState[HMnMPC];
EndIf[];

IfState[HMnMPC];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlBCmd, BCmdMap];
AddOut[PCtlABusCmd, ABusPAdd];
ReadRam1[SCmdLVM];
JmpState[HMnM11PC];

IfState[HMnM11PC];
ReadRam2[SCmdLVM];
JmpState[HMnM12PC];

IfState[HMnM12PC];
If[RamForP, T];
AddOut[PCtlSetNonFBTIP,	T];
AddOut[PCtlLdRBufDataLo,	T];
AddOut[PCtlLdRBufDataHi,	T];
ReadRam3[SCmdLVM];
JmpState[HMnM3PC];

If[RamForP, F];
ReadRam1[SCmdLVM];
JmpState[HMnM11PC];
EndIf[];

IfState[HMnM3PC];
JmpState[HMnM4PC];

IfState[HMnM4PC];
If[NonFBTIP, T];	And[TimeOut, F];
AddOut[PCtlCSCmd, SCmdVictim];
JmpState[HMnM4PC];

If[NonFBTIP, T];	And[TimeOut, T];
JmpState[StoreBTimeOutFaultPC];

If[NonFBTIP, F];	And[MyBFault, T];
AddOut[PCtlFault,	T];
AddOut[PCtlSelBFC,	T];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];

If[NonFBTIP, F];	And[MyBFault, F];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlBCmd, BCmdRB];
AddOut[PCtlCSCmd, SCmdVictim];
AddOut[PCtlABusCmd, ABusCam];
ReadRCam1[];
JmpState[HMRRCVct2PC];
EndIf[];

IfState[HM3nPPC];
If[AVM, T];	And[RCamForP, T];
ReadRCam2[SCmdLVM];
JmpState[HMRRCVM3PC];

If[AVM, T];	And[RCamForP, F];
ReadRCam1[];
JmpState[HM3nPPC];

If[AVM, F];
AddOut[PCtlABusCmd, ABusIOAId];
AddOut[PCtlWtMchVCam,	T];
JmpState[HMnMPC];
EndIf[];

IfState[HMRRCVM3PC];
If[RCamForP, T];
ReadRCam34[SCmdLVM];
JmpState[HMRRCVM4PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HM3nPPC];
EndIf[];

IfState[HMRRCVM4PC];
If[RCamForP, T];
ReadRCam34[SCmdLVM];
JmpState[HMRCamReadyPC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HM3nPPC];
EndIf[];

IfState[HMRCamReadyPC];
If[PAccessPerm, T];
AddOut[PCtlLdRBufHeader,	T];
AddOut[PCtlBCmd, BCmdRB];
AddOut[PCtlABusCmd, ABusCam];
AddOut[PCtlLdFlagsReg, T];
ReadRCam1[];
JmpState[HMRRCVct2PC];

If[PAccessPerm, F];
JmpState[StoreMemAccessFaultPC];
EndIf[];

IfState[HMRRCVct2PC];
If[RCamForP, T];
ReadRCam2[SCmdVictim];
JmpState[HMRRCVct3PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HMRRCVct2PC];
EndIf[];

IfState[HMRRCVct3PC];
If[RCamForP, T];
ReadRCam34[SCmdVictim];
JmpState[HMRRCVct4PC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HMRRCVct2PC];
EndIf[];

IfState[HMRRCVct4PC];
If[RCamForP, T];
ReadRCam34[SCmdVictim];
JmpState[HMReadRamPC];

If[RCamForP, F];
ReadRCam1[];
JmpState[HMRRCVct2PC];
EndIf[];

IfState[HMReadRamPC];
ReadRam1[SCmdVictim, NoDBus];
AddOut[PCtlABusCmd, ABusRCam];
AddOut[PCtlLdSnooperSetValid,	T];
JmpState[HMRR2PC];

IfState[HMRR2PC];
ReadRam2[SCmdVictim, NoDBus];
AddOut[PCtlDBusCmd, DBusABus];
AddOut[PCtlLdRBufDataLo,	T];
AddOut[PCtlLdRBufDataHi,	T];
JmpState[HMRR3PC];

IfState[HMRR3PC];
If[RPValid, T]; And[RamForP, T];
ReadRam3[SCmdVictim, NoDBus];
AddOut[PCtlLdFIFOSetFBTIP, T]; -- Ld FIFO If AOw - external gating
AddOut[PCtlBCmd, BCmdFB];
AddOut[PCtlABusCmd, ABusRCam];
JmpState[HMRR4PC];
If[RPValid, T]; And[RamForP, F];
ReadRam1[SCmdVictim, NoDBus];
AddOut[PCtlABusCmd, ABusRCam];
JmpState[HMRR2PC];
If[RPValid, F];
AddOut[PCtlSetNonFBTIP, T];
JmpState[HMReturn1PC];
EndIf[];

IfState[HMRR4PC];
AddOut[PCtlSetNonFBTIP, T];
JmpState[HMReturn1PC];

IfState[HMReturn1PC];
AddOut[PCtlABusCmd, ABusRqstBuf];
JmpState[HMReturn2PC];

IfState[HMReturn2PC];
If[NonFBTIP, T];	And[TimeOut, F];
AddOut[PCtlABusCmd, ABusRqstBuf];
AddOut[PCtlSelRplyData,	T];
JmpState[HMReturn2PC];

If[NonFBTIP, T];	And[TimeOut, T];
AddOut[PCtlSelRplyData,	T];
JmpState[StoreBTimeOutFaultPC];

If[NonFBTIP, F];	And[MyBFault, T];
AddOut[PCtlFault,	T];
AddOut[PCtlSelBFC,	T];
AddOut[PCtlReleaseP,	T];
AddOut[PCtlSelRplyData,	T];
JmpState[IdlePC]; -- check that fault code gets written automatically; if not, just do it in ucode by copying one of the store fault routines

If[NonFBTIP, F];	And[MyBFault, F];
AddOut[PCtlShftVictim, T];
JmpState[HMReturn3PC];
EndIf[];

IfState[HMReturn3PC];
AddOut[PCtlWtMchVCam,	T];
AddOut[PCtlABusCmd, ABusPAdd];
If[TopOfStack, FromRead];
AddOut[PCtlReleaseP,	T];
AddOut[PCtlSelRplyData,	T];
JmpState[IdlePC];

If[TopOfStack, FromWrite];
JmpState[HMReturn4PC];

If[f: TopOfStack, v: FromCWS, m: FromCWS]; -- TRUE if >= FromCWS=2
JmpState[HMReturn4PC];
EndIf[];

IfState[HMReturn4PC];
JmpState[HMReturn5PC];

IfState[HMReturn5PC];
AddOut[PCtlWtMchVCam,	T];
If[f: TopOfStack, v: FromWrite, m: FromCWS]; -- TRUE if < FromCWS=2
JmpState[PSRetryPC];

If[f: TopOfStack, v: FromCWS, m: FromCWS]; -- TRUE if >= FromCWS=2
JmpState[PCWSRetryPC];
EndIf[];

IfState[StoreMemAccessFaultPC];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultMemAccess];
JmpState[SMAF2PC];

IfState[SMAF2PC];
WriteRam2[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultMemAccess];
JmpState[SMAF3PC];

IfState[SMAF3PC];
If[RamForP, T];
WriteRam3[SCmdLVM, DBusABus];
AddOut[PCtlFault,	T];
AddOut[PCtlFaultCode, FaultMemAccess];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];

If[RamForP, F];
AddOut[PCtlDBusCmd, DBusABus];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultMemAccess];
JmpState[SMAF2PC];
EndIf[];

IfState[StoreBTimeOutFaultPC];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultBTimeOut];
JmpState[SBTOF2PC];

IfState[SBTOF2PC];
WriteRam2[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultBTimeOut];
JmpState[SBTOF3PC];

IfState[SBTOF3PC];
If[RamForP, T];
WriteRam3[SCmdLVM, DBusABus];
AddOut[PCtlFault,	T];
AddOut[PCtlFaultCode, FaultBTimeOut];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];

If[RamForP, F];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultBTimeOut];
JmpState[SBTOF2PC];
EndIf[];

IfState[StoreIOAccessFaultPC];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultIOAccess];
JmpState[SIOAF2PC];

IfState[SIOAF2PC];
WriteRam2[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultIOAccess];
JmpState[SIOAF3PC];

IfState[SIOAF3PC];
If[RamForP, T];
WriteRam3[SCmdLVM, DBusABus];
AddOut[PCtlFault,	T];
AddOut[PCtlFaultCode, FaultIOAccess];
AddOut[PCtlReleaseP,	T];
JmpState[IdlePC];

If[RamForP, F];
AddOut[PCtlDBusCmd, DBusABus];
WriteRam1[SCmdLVM, DBusABus];
AddOut[PCtlABusCmd, ABusFault+FaultIOAccess];
JmpState[SIOAF2PC];
EndIf[];

IfState[TestReadRamPC];
AddOut[PCtlForceWordAddress, T];
ReadRam1[SCmdVictim];
JmpState[TRR2PC];

IfState[TRR2PC];
AddOut[PCtlForceWordAddress, T];
ReadRam2[SCmdVictim];
JmpState[TRR3PC];

IfState[TRR3PC];
AddOut[PCtlForceWordAddress, T];
ReadRam3[SCmdVictim];
AddOut[PCtlLdRBufDataHi, T];
JmpState[IdlePC];

IfState[TestReadRCamPC];
ReadRCam1[];
JmpState[TRRC2PC];

IfState[TRRC2PC];
ReadRCam2[SCmdVictim];
JmpState[TRRC3PC];

IfState[TRRC3PC];
ReadRCam34[SCmdVictim];
JmpState[TRRC4PC];

IfState[TRRC4PC];
ReadRCam34[SCmdVictim];
JmpState[TRRC5PC];

IfState[TRRC5PC];
AddOut[PCtlABusCmd, ABusRCam];
JmpState[TRRC6PC];

IfState[TRRC6PC];
AddOut[PCtlDBusCmd, DBusABus];
AddOut[PCtlLdRBufDataHi, T];
JmpState[IdlePC];

IfState[TestReadVCamPC];
ReadVCam1[SCmdVictim];
JmpState[TRVC2PC];

IfState[TRVC2PC];
ReadVCam2[SCmdVictim];
JmpState[TRVC3PC];

IfState[TRVC3PC];
ReadVCam34[SCmdVictim];
JmpState[TRVC4PC];

IfState[TRVC4PC];
ReadVCam34[SCmdVictim];
JmpState[TRVC5PC];

IfState[TRVC5PC];
AddOut[PCtlABusCmd, ABusVCam];
JmpState[TRVC6PC];

IfState[TRVC6PC];
AddOut[PCtlDBusCmd, DBusABus];
AddOut[PCtlLdRBufDataHi, T];
JmpState[IdlePC];

IfState[TestShiftVictimPC];
AddOut[PCtlShftVictim, T];
JmpState[TSV2PC];

IfState[TSV2PC];
AddOut[PCtlFrzVictim, T];
JmpState[TSV3PC];

IfState[TSV3PC];
AddOut[PCtlFrzVictim, T];
JmpState[IdlePC];

IfState[TestResetVictimPC];
AddOut[PCtlResetVictim, T];
JmpState[TRV2PC];

IfState[TRV2PC];
AddOut[PCtlResetVictim, T];
JmpState[IdlePC];

fsm _ FSM.Finish[ctx];
fsm.outInAll	_ NOT usePC;
fsm.register	_ reg;
ct _ FSM.CodeMachine[fsm, impl]};

END.
-JSmallCachePmCodeFSM.mesa
Copyright c 1986 by Xerox Corporation.  All rights reserved.
Created: Douady, Sindhu April 10, 1987 12:50:16 pm PDT
Pradeep Sindhu October 27, 1987 12:15:49 pm PST
Cesar Douady May 13, 1987 3:09:46 pm PDT
Don Curry January 25, 1988 4:27:39 pm PST
Derived from SCPmCodeImpl.mesa 02-Dec-87 16:13:19 PST
Updated from SCPmCodeImpl.mesa 21-Jan-88 15:37:34 PST

This module defines the Processor-side microcode. Note that only the combinatorial part is modeled, and that the input, output, and feedback registers are within a higher level block defined by the schematic PCtl.sch.

In writing the microcode, we have made the following assumption about the speed of this combinatorial block: signals can go through the block in under one clock cycle, so that inputs need to come directly from a clocked register, and outputs need to go directly to a clocked register, with no intervening logic. This structure implies that the minimum delay between the microcode asserting a signal, and that signal having an effect on the input, is two cycles. This minimum delay is, in fact, used for the signal PCtlSetNonFBTIP -> NonFBTIP.
Microcode States
Constants
Declare the finite state machine generation procs
Constants
Stack Addresses
ABus Source Codes
forbidden:						NAT = 5;
DBus Source Codes
Array Multiplexer Select Codes
PCmd Defs
BCmd Defs
Fault Code Defs
Input Declarations
Output Declarations
Useful micro procs
This corresponds to the ReadRCam command cycle
This corresponds to the first cycle of RCam use
This corresponds to the second and third cycles of RCam use (note they are the same)
This corresponds to the ReadVCam command cycle
This corresponds to the first cycle of VCam use
This corresponds to the second and third cycles of VCam use (note they are the same)
This corresponds to the ReadRam command cycle
This corresponds to the first cycle of Ram use (note that ReadRam2 must follow ReadRam1
AddOut[PCtlRSCmd, sCmd];
This corresponds to the second cycle of Ram use
This corresponds to the WriteRam command cycle
This corresponds to the first cycle of Ram use (note that WriteRam2 must follow ReadRam1
This corresponds to the second cycle of Ram use
The microcode
Stack bits are initialized to keep Rosemary happy
Hit: Everything is done automatically
A miss: Do partial virtual match to find translation
A hit: Check if shared bit is set; Wait for ASh to be available
A miss: Do partial virtual match to find translation
A hit: Good, get the old value
A miss: Do partial virtual match to find translation
A hit: Everything is done automatically
A miss: Check if we have access permission; First match without flags
A hit: Everything is done automatically
A miss: Check if we have access permission; First match without flags
This operation always misses: Load RqstBuf header with IO address; Send ArbRequest; Set NonFBTIP (continuation is the same as IOWrite)
This operation always misses: Load RqstBuf header with IO address; Send ArbRequest; Set NonFBTIP (continuation is the same as IOWrite)
Wait virtual match w/o flags to complete, 1 of 3
Wait virtual match w/o flags to complete, 2 of 3
Wait virtual match w/o flags to complete, 3 of 3
Partial match successful: an IO access permission fault, store it and return
A miss. Generate IO(Read/Write) Rqst packet: Load RqstBuf header with IO address; Load RqstBuf data with PData (doesn't hurt for read); Send ArbRqst; Set NonFBTIP; Return when transaction completes (same as PS)
Wait for reply to come back
A timeOut: Signal and store in the array (can be done after releasing processor)
Reply came back with a fault, release processor and return
Reply came back normally, release processor and return
Wait for AVM, 1 of 3: Don't need Ram value, just want to verify a hit
Wait for AVM, 2 of 3
Wait for AVM, 3 of 3: Read Ram to get the old value
A hit: Wait for PCWSEq, 1 of 3; (Can't let the processor go, sample value may be wrong)
A miss: Do partial virtual match to find translation
Wait for PCWSEq, 2 of 3: Compare old and sample; Put old in RqstBuf in case shared is set
Ratted! Just redo it: Read Ram to get the old value
Wait for PCWSEq, 3 of 3
Read new value from the Ram, present IOAddress to VCam
Not equal: Don't need to do anything
Read new value from the Ram, send ReadRam pulse
Wait for data to appear in RRdLatch, 1 of 2
Wait for data to appear in RRdLatch, 2 of 2: Start writing new data back; Load Rqst Buffer with new value in case shared bit is set
Ratted! Re-read new value from scrtach; Present IOAddress to VCam
Select RamReadLatch to go to the Ram, 1 of 2
Wait for Ash, 1 of 3
Select RamReadLatch to go to the Ram, 2 of 2; Wait for Ash, 2 of 3; Start RCam read in case of ASh
Ratted! Re-read the new value from scratch; Present IOAddress to VCam
Wait for Ash, 3 of 3; Read RCam, cycle 1
Data is shared, generate CWSRqst; Read RCam to get real address, cycle 2
Don't have RCam; Read RCam to get real address, cycle 1
Data is not shared, we are done
First, read RCam to get the real address, cycle 2
First, read RCam to get the real address, cycle 1
Read RCam, cycle 3; We have the RCam, go to next cycle
Read RCam, cycle 1; We don't have the RCam, return to cycle 2
Read RCam, cycle 4; RCam has been read; Send ArbRqst; Set NonFBTIP
Read RCam, cycle 1; We don't have the RCam, return to cycle 2
Load RqstBuf header with real address
Wait for AVM, 1 of 3; Write Ram in case of a match
Wait for time to pass
A miss: Do partial virtual match to find translation
Wait for AVM, 2 of 3
Wait for AVM, 3 of 3
Ratted! Just redo it; Write the Ram in case of a match
A hit: Check for shared bit; Wait for ASh to be available
A miss: Do partial virtual match to find translation
Data is shared, generate WSRqst; Read RCam to get the real address
Data is not shared, everything is done automatically: Release processor
Read RCam, cycle 2: We have RCam, go to next cycle
Read RCam, cycle 1: We don't have RCam, return to cycle 2
Read RCam, cycle 3: We have RCam, go to next cycle
Read RCam, cycle 1: We don't have RCam, return to cycle 2
Read RCam, cycle 4: RCam has been read; Send ArbRqst; Set NonFBTIP
Read RCam, cycle 1: We don't have RCam, return to cycle 2
Load Rqst buffer header with real address
Blow one cycle to give NonFBTIP time to be set
Wait for WSRply, IOWRply, IORRply, BIOWRply, DeMapRply
A timeOut: Signal and return
WSRply has come back with a fault, release processor and return
Reply has come back, release processor and return
Wait for partial virtual match, 1 of 3: (Could begin the RCam read here at the expense of (~6) more lines) Freeze victim, Cycle 1 of 2
Note: The index i in HMiPC refers to time, not cycle number
Wait for partial virtual match, 2 of 3: Initiate RCam read in case partial match succeeds, Read RCam cycle 1; Freeze victim, Cycle 2 of 2
Wait for partial virtual match, 3 of 3; Read RCam, cycle 2
Wait for partial virtual match, 3 of 3; Don't have RCam, Read RCam, cycle 1
Partial virtual match is successful; Read RCam, cycle 3
Partial virtual match is successful; Don't have RCam, Read RCam, cycle 1
Read AId from the Ram, first do a match in the VCam. Note that this destroys the old contents of the vCamWtReg, which be restored automatically by the hardwired control when the MapRply comes back (see VCamInterlockCtl).
Read AId from Ram, cycle 1; Load RqstBuf with MapRqst|myId|PAdd; Set NonFBTIP
Read AId from Ram, cycle 2; Wait for AId to appear in the RRdLatch, 1 of 1
Load RBufLo with AId, RBufHi with garbage; Send ArbRqst
Ratted, didn't have Ram! Just redo it
Blow one cycle to let NonFBTIP get set
Wait for MapRply to come back.
TimeOut : Signal and store the fault in the array
MapCache fault: abort access
Load Rqst buffer header with RealAddress; Read RCam using victim, cycle 1; Set CSCmd to select Victim so we can drive the cam (rcampage+vcamblock) onto the ABus (note that ReadRCam1 does not set the CSCmd).
For all jumps to this location except the one from HM2PC, we know that the AVM check will succeed since match is latched, and AVM was high earlier. Doing the check in all cases allows us to share this instruction, thereby eliminating waste.
Partial virtual match is successful; Read RCam, cycle 2
Partial virtual match is successful; Didn't have RCam, Read RCam, cycle 1
Read AId from the Ram, first find it in the VCam
Read RCam, cycle 3
Read RCam, cycle 1; Didn't have RCam, redo read
Read RCam, cycle 4; RCam has been read
Read RCam, cycle 1; Didn't have RCam, redo read
We've read RPage from the RCam successfully
Load RqstBuf header with RealAddress; Load FlagsReg; Read RCam using victim, cycle 1.
Fault: Signal and store in the array (can be done after releasing processor)
Read RCam using victim, cycle 2
Read RCam, cycle 1; Didn't have RCam, return to cycle 2
Read RCam using victim, cycle 3
Read RCam, cycle 1; Didn't have RCam, return to cycle 2
Read RCam using victim, cycle 4
Read RCam, cycle 1; Didn't have RCam, return to cycle 2
ABus _ VictimAddress (note ABus _ AToDPipe Reg automatically); Load Snooper in case of FlushBlock; Set snooper valid to begin snooping;
RqstBufLo _ AToDPipe; RqstBufHi _ garbage; ReadRam cycle 2
Read Ram, cycle 3; LoadFIFOIfAOw; Generate FBRqst
Redo Ram Read; Also redrive victim address onto ABus
Victim is not valid, don't flush it.
Send RBRqst; Set NonFBTIP;
Send RBRqst; Set NonFBTIP;
Wait a cycle to let NonFBTIP get set; ABus_RealAddress to load Snooper on MyRBRqst
Wait for RBRply; ABus_RealAddress to load Snooper on MyRBRqst
TimeOut: Signal and store the fault in the array
Reply has come back with a fault, release processor and return
Produce the pulse to write the VCam and Flags (recall that VCamWtReg may have been overwritten with the address of IOAID).
Release processor and go to idle
Wait two cycles because we can't use the VCam to do a match yet
Wait two cycles because we can't use the VCam to do a match yet
Wait one cycle because we can't use the VCam to do a match yet
Do a Match to check if address is in array
Do a Match to check if address is in array
Write fault code into the RAM, cycle 1
Write fault code into the RAM, cycle 2
Write completed successfully. Go back to Idle loop
Ratted! Redo the access
Write fault code into the RAM, cycle 1
Write fault code into the RAM, cycle 2
Write completed successfully. Go back to Idle loop
Ratted! Redo the access
Write fault code into the RAM, cycle 1
Write fault code into the RAM, cycle 2
Write completed successfully. Go back to Idle loop
Ratted! Redo the access
Here begins the tests subroutines. They cannot be executed during normal operations. They are reached only by the mean of a TestCode forced by the DebugBus. It is assumed that the DynaBus is stopped during these operations.

Read RCam using Victim, cycle 1
Read RCam using Victim, cycle 2
Read RCam using Victim, cycle 3
Read RCam using Victim, cycle 4
Put Victim into the ABus to DBus pipe (automatic) through the ABus
Load RBufDataLo with the content of the RCam
Read VCam using Victim, cycle 1
Read VCam using Victim, cycle 2
Read VCam using Victim, cycle 3
Read VCam using Victim, cycle 4
Put Victim into the ABus to DBus pipe (automatic) through the ABus
Load RBufDataLo with the content of the VCam
The victim is assumed to be waiting at some place
The victim may point to a place where it wants to get out of
Force it to stay there. Cycle 1 of 2
The victim may point to a place where it wants to get out of
Force it to stay there. Cycle 2 of 2
Force the victim to point at the initial place. Cycle 1 of 2
Force the victim to point at the initial place. Cycle 2 of 2
The victim will not get out now that the used bit has been cleared
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