( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	x	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	x	x	xx x
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	x	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	x	x	xx x

( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x

( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x

( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	x	0	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x

( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x 

( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x	--A 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x	--B 
( 0 0 0 1 0 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	x	xxxx	x	x	x	x	0	0	x	xx x 

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x

( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	0	0	xxxx	0	0	0	0	0	0	x	xx x 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x 

( 0 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 1 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 1 0 1 1 1 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 1 1 0 1 1 1 )	0	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x

( 0 0 0 1 1 1 )	1	0	0000	0	0	0	0	0	0	00	|	x	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 1 0 0 1 1 1 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 1 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--A 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x	--B 
( 0 0 0 1 1 0 )	1	0	0000	0	0	0	0	0	0	00	|	1	0	xxxx	0	0	0	0	0	0	x	xx x


( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	9	F	AC	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	9	F	AC	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	9	F	45	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	202E	0	0	0	0	0	0	45	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0034	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	2078	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0055	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	2039	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0071	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	20D7	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0017	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	282E	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0011	0	0	0	0	0	0	xx	|	x	0	xxxx	0	1	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	2878	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0044	0	0	0	0	0	0	xx	|	x	0	xxxx	0	1	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	2839	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0075	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	1	28AD	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0039	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	39	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	39	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	75	x

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	AC	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	AC	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	45	x

( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	AD	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --A 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	AD	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	8	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	xx	x --B 
( 0 0 0 1 1 0 )	0	0	0000	0	0	0	0	0	0	xx	|	x	0	xxxx	0	0	0	0	0	0	x	39	x



.

μSmallCacheInner-WriteSingles.oracle
Pradeep Sindhu May 6, 1988 11:33:58 pm PDT
TEST COMPLETE


NB: Each line corresponds to one cycle of the DynaBus clock

The state of the cache following Reset is: all x's except for signals set otherwise by the hardware
_ Logic.SetOracleFileName["SmallCacheInnerTest", "SmallCacheInner-WriteSingles"]
_ SmallCacheLogic.ArrayPutState[SmallCacheLogic.cacheStateValueH]



Perform the reset sequence:
Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6):
Pradeep Sindhu May 6, 1988 6:28:09 pm PDT

  D D D n n D	  D	B	B		G	G	I	P	P	P	P		|	D	H	B		B	B	R	S	P	P	P	P  P
  S A E D D S	  S	C	D		L	r	S	m	C	B	D		|	B	d	D		O	S	e	S	R	F	F	D  R
  h d x F R e	  e	y	a		e	a	S	o	m	y	a		|	u	r	a		w	h	q	t	e	a	a	a  e
  i d e r e r	  l	c	t		n	n	t	d	d	t	t		|	s	C	t		n	a	u	o	j	u	u	t  s
  f r c e s i	  e	l	a		g	t	o	e	I	e	a		|	O	y	a		e	r	e	p	e	l	l	a  c
  t e u e e a	  c	e	I		t		p	I	n	S			|	u	c	O		r	e	s	O	c	t	t	   h
  C s t z t l	  t	0	n		h		I	n		e			|	t	l	u		O	d	t	u	t		C	   e
  k s e e   I	 							n			l			|		e	t		u	O		t			o	   d
            n											I			|		O			t	u					d	   u
															n			|		u				t					e	   l
																		|		t											e
																		|														


Check that chip Id can be read out (scan path 0):
  D D D n n D	  D	B	B		G	G	I	P	P	P	P		|	D	H	B		B	B	R	S	P	P	P	P  P
  S A E D D S	  S	C	D		L	r	S	m	C	B	D		|	B	d	D		O	S	e	S	R	F	F	D  R
  h d x F R e	  e	y	a		e	a	S	o	m	y	a		|	u	r	a		w	h	q	t	e	a	a	a  e
  i d e r e r	  l	c	t		n	n	t	d	d	t	t		|	s	C	t		n	a	u	o	j	u	u	t  s
  f r c e s i	  e	l	a		g	t	o	e	I	e	a		|	O	y	a		e	r	e	p	e	l	l	a  c
  t e u e e a	  c	e	I		t		p	I	n	S			|	u	c	O		r	e	s	O	c	t	t	   h
  C s t z t l	  t	0	n		h		I	n		e			|	t	l	u		O	d	t	u	t		C	   e
  k s e e   I	 							n			l			|		e	t		u	O		t			o	   d
            n											I			|		O			t	u					d	   u
															n			|		u				t					e	   l
																		|		t											e
																		|														
Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in):
  D D D n n D	  D	B	B		G	G	I	P	P	P	P		|	D	H	B		B	B	R	S	P	P	P	P  P
  S A E D D S	  S	C	D		L	r	S	m	C	B	D		|	B	d	D		O	S	e	S	R	F	F	D  R
  h d x F R e	  e	y	a		e	a	S	o	m	y	a		|	u	r	a		w	h	q	t	e	a	a	a  e
  i d e r e r	  l	c	t		n	n	t	d	d	t	t		|	s	C	t		n	a	u	o	j	u	u	t  s
  f r c e s i	  e	l	a		g	t	o	e	I	e	a		|	O	y	a		e	r	e	p	e	l	l	a  c
  t e u e e a	  c	e	I		t		p	I	n	S			|	u	c	O		r	e	s	O	c	t	t	   h
  C s t z t l	  t	0	n		h		I	n		e			|	t	l	u		O	d	t	u	t		C	   e
  k s e e   I	 							n			l			|		e	t		u	O		t			o	   d
            n											I			|		O			t	u					d	   u
															n			|		u				t					e	   l
																		|		t											e
																		|														
SmallCacheInner-WriteSingles:
NB: Our chip's Id=1, so Id in packet must be 0 to indicate a Foreign device

First write to line 4 word 4 so as to set the owner bit (none of the lines have owner set)
PWriteHit[AC] (line 4 word 4):

WriteSingleRequest-Foreign-Miss 

WriteSingleRequest-Foreign-Miss 

WriteSingleRequest-Foreign-Hit (hits line 0, should pull shared line)

WriteSingleRequest-Foreign-Hit (hits line 7, should pull shared line)

WriteSingleReply-Foreign-Miss 
WriteSingleReply-Foreign-Miss 
WriteSingleReply-Foreign-Hit (line 0)
WriteSingleReply-Foreign-Hit (line 4)
Check that the locations we wrote into did get written
PReadHit[39]:
PReadHit[AC]:
PReadHit[AD]:
The state of the cache at this point should be: SmallCacheArrayStateValues.cacheStateValueI

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