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ÚSmallCacheInner-ReadBlocks.oracle Pradeep Sindhu May 6, 1988 11:31:43 pm PDT TEST COMPLETE NB: Each line corresponds to one cycle of the DynaBus clock The state of the cache following Reset is: all x's except for signals set otherwise by the hardware _ Logic.SetOracleFileName["SmallCacheInnerTest", "SmallCacheInner-ReadBlocks"] _ SmallCacheLogic.ArrayPutState[SmallCacheLogic.cacheStateValueA] Perform the reset sequence: Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6): Pradeep Sindhu May 6, 1988 6:28:09 pm PDT D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Check that chip Id can be read out (scan path 0): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | SmallCacheInner-ReadBlocks: NB: Our chip's Id=1, so Id in packet must be 0 to indicate a Foreign device First write to line 7 word 7 so as to set the owner bit (none of the lines have owner set) PWriteHit[AC] (line 7 word 7); write whatever is there already since we just want to set owner: ReadBlockRequest-Foreign-Miss ReadBlockRequest-Foreign-Miss ReadBlockRequest-Foreign-Hit (hits line 2, should set shared bit and assert shared line) ReadBlockRequest-Foreign-Hit (hits line 7, should set shared bit, assert shared and owner lines and reply with the data) Give the grant for the RBRply ReadBlockReply-Foreign-Miss ReadBlockReply-Foreign-Miss ReadBlockReply-Foreign-Hit (line 0) ReadBlockReply-Foreign-Hit (line 4) PWriteHit-Shared[52] with someone pulling shared on the WSRqst Here'e our own WSRqst on our input wires And through the magic of a virtual MemController, here's the WSRply on our input wires PReadHit[52]: PWriteHit-Shared[52] with no one pulling shared on the WSRqst (ie. shared will get cleared) Here'e our own WSRqst on our input wires And through the magic of a virtual MemController, here's the WSRply on our input wires PReadHit[52]: The state of the cache at this point should be: SmallCacheArrayStateValues.cacheStateValueG ťĘ ,šś!™!Icode™*—JJ™ J™J™J™;J™šśc™cJšśN™NJšśA™AJ™—J™J™šĎf™Jšť–™–K™)J™Jšť%Đefť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť#žť™?Jšť"žť™=Jšťžť™5Jšťžť™1Jšťžť™'Jšťžť™"JšĐfzŃefzź ™!J™JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťFFJJšťJJJšťFFJšťJJJšťFFJJšťJJJšťFFJšťJJJšťFF—J™šť1™1Jšť%žť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť#žť™?Jšť"žť™=Jšťžť™5Jšťžť™1Jšťžť™'Jšťžť™"Jšź ź ™!JšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFFJšťJJJšťFF—Jšťf™fJšť%žť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť%žť™AJšť#žť™?Jšť"žť™=Jšťžť™5Jšťžť™1Jšťžť™'Jšťžť™"Jšź ź ™!JšťJJJšťEEJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJšťJJJšťEE—JJIheadšś™J™KJ™J™Z™_JšťJJJšťEEJšťJJJšťEE—J™J™™JšťJJJšťEEJšťJJJšťEE—J™™JšťJJJšťEEJšťJJJšťEE—J™™XJšťJJJšťEEJšťJJJšťEE—J™™xJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJJ™JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJ—J™™JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEE—J™™JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEE—J™™#JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJ—J™™#JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJ—™>JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJ™(JšťJJJšťEEJšťJJJšťEEJJ™VJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJ—™ JšťJJJšťEEJšťJJJšťEEJ—™[JšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJ™(JšťJJJšťEEJšťJJJšťEEJJ™VJšťJJJšťEEJšťJJJšťEEJJšťJJJšťEEJšťJJJšťEEJJ—™ JšťJJJšťEEJšťJJJšťEE—JJJJJšś[™[J™J—…—>’W