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0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 2 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 1 xxxx 0 0 0 0 1 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 1 xxxx 0 0 0 0 1 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 1 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 1 0 0 0 0 xx | x 1 013F 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x --B ( 0 0 0 1 1 0 ) 0 1 013F 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x --B ( 0 0 0 1 1 0 ) 0 1 093F 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x xx x ( 0 0 0 1 1 0 ) 0 0 FFCC 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 DD00 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 3476 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x CC x --B ( 0 0 0 1 1 0 ) 0 0 7174 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x CC x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x CC x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 1 0 x CC x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CC x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 52 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 52 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x BA x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 58 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 58 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x AA x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 8F | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 8F | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 66 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 AF | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 AF | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x CD x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 CC | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 CC | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 1A x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 D7 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 D7 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x DE x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 25 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 25 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 11 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 39 | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 39 | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 8 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x 00 x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --A ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x --B ( 0 0 0 1 1 0 ) 0 0 0000 0 0 0 0 0 0 xx | x 0 xxxx 0 0 0 0 0 0 x xx x . -SmallCacheInner-InitialReads.oracle Pradeep Sindhu May 6, 1988 6:30:50 pm PDT TEST COMPLETE NB: Each line corresponds to one cycle of the DynaBus clock The state of the cache following Reset is: all x's except for signals set otherwise by the hardware _ Logic.SetOracleFileName["SmallCacheInnerTest", "SmallCacheInner-InitialReads"] _ SmallCacheLogic.ArrayPutState[NIL] Perform the reset sequence: Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6): Pradeep Sindhu May 6, 1988 6:28:09 pm PDT D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Check that chip Id can be read out (scan path 0): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in): D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | SmallCacheInner-InitialReads: First Write the AID register: D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Write AID [09], Kernel Mode: Read it back to check it [09]: Now do PReads to fill the cache: D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | PReadMiss-MapMiss-NoVictim[50]: Let the grant come here, so we send our MapRqst Here's our map request on our input wires, followed immediately by the MapRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply PReadMiss-MapHit-NoVictim[59]: Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | PReadMiss-MapMiss-NoVictim[8A]: Let the grant come here, so we send our MapRqst Here's our map request on our input wires, followed immediately by the MapRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply PReadMiss-MapHit-NoVictim[AB]: Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | PReadMiss-MapMiss-NoVictim[CC]: Let the grant come here, so we send our MapRqst Here's our map request on our input wires, followed immediately by the MapRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply PReadMiss-MapHit-NoVictim[D5]: Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | PReadMiss-MapMiss-NoVictim[26]: Let the grant come here, so we send our MapRqst Here's our map request on our input wires, followed immediately by the MapRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply PReadMiss-MapHit-NoVictim[3F]: Give the grant for the RBRqst Here's our RBRqst on our input wires And shortly thereafter the RBRply D D D n n D D B B G G I P P P P | D H B B B R S P P P P P S A E D D S S C D L r S m C B D | B d D O S e S R F F D R h d x F R e e y a e a S o m y a | u r a w h q t e a a a e i d e r e r l c t n n t d d t t | s C t n a u o j u u t s f r c e s i e l a g t o e I e a | O y a e r e p e l l a c t e u e e a c e I t p I n S | u c O r e s O c t t h C s t z t l t 0 n h I n e | t l u O d t u t C e k s e e I n l | e t u O t o d n I | O t u d u n | u t e l | t e | Now read one word from each of the lines 7, 6, 5, 4, 3, 2, 1, and 0 PReadHit[52]: PReadHit[58]: PReadHit[8F]: PReadHit[AF]: PReadHit[CC]: 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