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xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 D F 00000033 | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x --B ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 0 0 00000033 | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 C 0 00000009 | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x --A ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 C 0 00000009 | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 C 0 xxxxxxxx | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x xxxxxxxx x --B ( 0 1 1 0 0 0 ) 0 0 0000000000000000 0 0 0 0 0 0 xxxxxxxx | x 0 xxxxxxxxxxxxxxxx 0 0 0 0 0 0 x 00000033 x . (SmallCache.oracle Pradeep Sindhu April 28, 1988 0:59:10 am PDT This oracle file does a very simple test on the top level. NB: Each line corresponds to one cycle of the DynaBus clock The state of the cache following Reset is: all x's except for signals set otherwise by the hardware Perform the reset sequence: Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6): D n n D D D D B B G G I P P P P | D H B B B R S P P P P P S D D E A S S C D L r S m C B D | B d D O S e S R F F D R e R F x d h e y a e a S o m y a | u r a w h q t e a a a e r e r e d i l c t n n t d d t t | s C t n a u o j u u t s i s e c r f e l a g t o e I e a | O y a e r e p e l l a c a e e u e t c e I t p I n S | u c O r e s O c t t h l t z t s C t 0 n h I n e | t l u O d t u t C e I e e s k n l | e t u O t o d n n I | O t u d u n | u t e l | t e | Check that chip Id can be read out (scan path 0): D n n D D D D B B G G I P P P P | D H B B B R S P P P P P S D D E A S S C D L r S m C B D | B d D O S e S R F F D R e R F x d h e y a e a S o m y a | u r a w h q t e a a a e r e r e d i l c t n n t d d t t | s C t n a u o j u u t s i s e c r f e l a g t o e I e a | O y a e r e p e l l a c a e e u e t c e I t p I n S | u c O r e s O c t t h l t z t s C t 0 n h I n e | t l u O d t u t C e I e e s k n l | e t u O t o d n n I | O t u d u n | u t e l | t e | Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in): D n n D D D D B B G G I P P P P | D H B B B R S P P P P P S D D E A S S C D L r S m C B D | B d D O S e S R F F D R e R F x d h e y a e a S o m y a | u r a w h q t e a a a e r e r e d i l c t n n t d d t t | s C t n a u o j u u t s i s e c r f e l a g t o e I e a | O y a e r e p e l l a c a e e u e t c e I t p I n S | u c O r e s O c t t h l t z t s C t 0 n h I n e | t l u O d t u t C e I e e s k n l | e t u O t o d n n I | O t u d u n | u t e l | t e | First Write the AID register: D n n D D D D B B G G I P P P P | D H B B B R S P P P P P S D D E A S S C D L r S m C B D | B d D O S e S R F F D R e R F x d h e y a e a S o m y a | u r a w h q t e a a a e r e r e d i l c t n n t d d t t | s C t n a u o j u u t s i s e c r f e l a g t o e I e a | O y a e r e p e l l a c a e e u e t c e I t p I n S | u c O r e s O c t t h l t z t s C t 0 n h I n e | t l u O d t u t C e I e e s k n l | e t u O t o d n n I | O t u d u n | u t e l | t e | Write AID [09], Kernel Mode: Read it back to check it [09]: ÊÄ˜šœ™Icode™,—J˜J™:J™J™;J™Jšœc™cJ™šÏf™Jš–™–J™Jš)Ðef™KJš)ž™KJš)ž™KJš)ž™KJš)ž™KJš'ž™IJš&ž™GJš!ž™?Jšž™;Jšž™1Jšž™,JšÐfzÑefzŸ™,J™Jšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJšj˜jJ˜Jšn˜nJšj˜jJšn˜nJšj˜jJ˜Jšn˜nJšj˜jJšn˜nJšj˜j—J˜š1™1Jš)ž™KJš)ž™KJš)ž™KJš)ž™KJš)ž™KJš'ž™IJš&ž™GJš!ž™?Jšž™;Jšž™1Jšž™,JšŸ Ÿ™,Jšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜jJšn˜nJšj˜j—J™šf™fJš)ž™KJš)ž™KJš)ž™KJš)ž™KJš)ž™KJš'ž™IJš&ž™GJš!ž™?Jšž™;Jšž™1Jšž™,JšŸ Ÿ™,Jšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJ˜Jšn˜nJši˜iJšn˜nJši˜iJšn˜nJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜iJšm˜mJši˜i—J˜J™š™Jš)ž™KJš)ž™KJš)ž™KJš)ž™KJš)ž™KJš'ž™IJš&ž™GJš!ž™?Jšž™;Jšž™1Jšž™,JšŸ Ÿ™,š™Jšn˜nJši˜iJšn˜nJši˜i—J™š™Jšn˜nJši˜iJšn˜nJši˜i—J™—J™Jš˜J˜—…—-ÜBÈ