( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	x	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	x	x	xxxxxxxx x
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	x	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	x	x	xxxxxxxx x

( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x

( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x

( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	x	0	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x

( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x 

( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x	--A 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x	--B 
( 0 0 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	x	x	x	x	0	0	x	xxxxxxxx x 

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 

( 0 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x

( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	0	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x 
( 0 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 0 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 1 0 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 1 1 1 0 1 1 )	0	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x

( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--A 
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x	--B 
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --A
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --B
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --A
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --B
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --A
( 0 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --B
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 1 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --A
( 1 1 1 0 0 1 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --B
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --A
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x --B
( 0 1 1 0 0 0 )	1	0	0000000000000000	0	0	0	0	0	0	00000000	|	1	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	C	F	20000002	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	C	F	20000002	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	C	F	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	2	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	1	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	1	0	0	0	0	xxxxxxxx	|	x	1	8199800020000002	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	0	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	1	8199800020000002	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	1	8999800020000002	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000001234567	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	01234567	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	D	F	20000002	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	D	F	20000002	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	D	F	01234567	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	01234567	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x

( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x --A 
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	0	0	x	xxxxxxxx	x
( 0 1 1 0 0 0 )	0	0	0000000000000000	0	0	0	0	0	0	xxxxxxxx	|	x	x	xxxxxxxxxxxxxxxx	0	0	0	0	1	0	x	xxxxxxxx	x --B 
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'RSmallCache-PAll.oracle
Pradeep Sindhu May 14, 1988 7:19:23 pm PDT
Don Curry May 23, 1988 1:57:07 pm PDT

NB: Each line corresponds to one cycle of the DynaBus clock

The state of the cache following Reset is: all x's except for signals set otherwise by the hardware
_ Logic.SetOracleFileName["SmallCacheInnerTest", "SmallCacheInner-PAll"]

Perform the reset sequence:
Assert Reset till x's get flushed out (the last signal appears to be RamForP, which settles 3 cycles after BCtlRamForBCWS6, which settles in cycle 6):

  D n n D D D	  D	B	B						G	G	I	P	P	P	P				|	D	H	B						B	B	R	S	P	P	P	P  P
  S D D E A S	  S	C	D						L	r	S	m	C	B	D				|	B	d	D						O	S	e	S	R	F	F	D  R
  e R F x d h	  e	y	a						e	a	S	o	m	y	a				|	u	r	a						w	h	q	t	e	a	a	a  e
  r e r e d i	  l	c	t						n	n	t	d	d	t	t				|	s	C	t						n	a	u	o	j	u	u	t  s
  i s e c r f	  e	l	a						g	t	o	e	I	e	a				|	O	y	a						e	r	e	p	e	l	l	a  c
  a e e u e t	  c	e	I						t		p	I	n	S					|	u	c	O						r	e	s	O	c	t	t	   h
  l t z t s C	  t	0	n						h		I	n		e					|	t	l	u						O	d	t	u	t		C	   e
  I   e e s k	 											n			l					|		e	t						u	O		t			o	   d
  n         n															I					|		O							t	u					d	   u
																			n					|		u								t					e	   l
																								|		t															e
																								|																			

Check that chip Id can be read out (scan path 0):

Shift In MyId (scan path 1) (Recall that MyId is only one bit so only one bit needs to be shifted in):

SmallCacheInner-IO Miss:
IO Read Miss:
IO Read [30], Kernel Mode:
Let the grant come here, so we send our IOReadRqst
Here's our IOReadRqst on our input wires, followed immediately by the IOReadRply
IO Write Miss:
IO Write Miss [30], Kernel Mode:
Let the grant come here, so we send our IOWriteRqst
Here's our IOWriteRqst on our input wires, followed immediately by the IOWriteRply
SmallCacheInner-InitialReads:
First Write the AID register:
Write AID [09], Kernel Mode:

Read it back to check it [09]:


Now do PReads to fill the cache:

PReadMiss-MapMiss-NoVictim[51275400]:
Let the grant come here, so we send our MapRqst
Here's our map request on our input wires, followed immediately by the MapRply
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply


PReadMiss-MapHit-NoVictim[51275419]:
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply

PReadMiss-MapMiss-NoVictim[ABEF575A]:
Let the grant come here, so we send our MapRqst
Here's our map request on our input wires, followed immediately by the MapRply
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply
PReadMiss-MapHit-NoVictim[ABEF571B]:
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply
PReadMiss-MapMiss-NoVictim[175792CC]:
Let the grant come here, so we send our MapRqst
Here's our map request on our input wires, followed immediately by the MapRply
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply

PReadMiss-MapHit-NoVictim[17579215]:
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply

PReadMiss-MapMiss-NoVictim[73FFAF06]:
Let the grant come here, so we send our MapRqst
Here's our map request on our input wires, followed immediately by the MapRply
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply

PReadMiss-MapHit-NoVictim[73FFAF17]:
Give the grant for the RBRqst
Here's our RBRqst on our input wires
And shortly thereafter the RBRply


Now read one word from each of the lines 7, 6, 5, 4, 3, 2, 1, and 0
PReadHit[51275402]:
PReadHit[51275418]:
PReadHit[ABEF575B]:
PReadHit[ABEF571C]:
PReadHit[175792CD]:
PReadHit[17579216]:
PReadHit[73FFAF07]:
PReadHit[73FFAF11]:
We add the following cycles to let the victim reach a stable value
The state of the cache at this point should be: SmallCacheArrayStateValues.cacheStateValueA
SmallCacheInner-Writes:
Do Word writes to each of the lines
PWriteHit[51275402] (line 7):
PWriteHit[51275419] (line 6):
PWriteHit[ABEF575B] (line 5):
PWriteHit[ABEF571F] (line 4):
PWriteHit[175792C8] (line 3):
PWriteHit[17579214] (line 2):
PWrite-NoWritePermission[73FFAF05] (line 1):

PWrite-NoWritePermission[73FFAF17] (line 0):


Then read them back to verify the contents
PReadHit[51275402]:
PReadHit[51275419]:
PReadHit[ABEF575B]:
PReadHit[ABEF571F]:
PReadHit[175792C8]:
PReadHit[17579214]:
PReadHit[73FFAF05]:
PReadHit[73FFAF17]:


Do Byte writes to each of the lines (write FF to word and then clear one or more bytes); for one of the byte writes make sure that the byte data has zeros in only the bytes were trying to write to ensure we weren't just lucky.
PWriteHit[51275402]:
PWriteHit[51275402]:
PWriteHit[51275419]:
PWriteHit[51275419]:
PWriteHit[ABEF575B]:
PWriteHit[ABEF575B]:
PWriteHit[ABEF571F]:
PWriteHit[ABEF571F]:
PWriteHit[175792C8]:
PWriteHit[175792C8]:
PWriteHit[17579214]:
PWriteHit[17579214]:

Read the words back to verify the contents
PReadHit[51275402]:
PReadHit[51275419]:
PReadHit[ABEF575B]:
PReadHit[ABEF571F]:
PReadHit[175792C8]:
PReadHit[17579214]:
PReadHit[73FFAF05]:
PReadHit[73FFAF17]:
Add cycles to let the victim stabilize:

The victim should now be pointing to line 1. Next, reference line 1 to push victim to line 0:
PReadHit[73FFAF06]:
The state of the cache at this point should be: SmallCacheArrayStateValues.cacheStateValueB

SmallCacheInner-WriteMisses:
Do a write miss
PWriteMiss-MapHit-NoVictim(5127544F)
Give the grant for the RBRqst
Here's our RBRqst on our input wires
Let the RBRply come here
Now read the word just written, and the other words from the block fetched
PReadHit[5127544F]:
PReadHit[51275448]:
PReadHit[51275449]:
PReadHit[5127544A]:
PReadHit[5127544B]:
PReadHit[5127544C]:
PReadHit[5127544D]:
PReadHit[5127544E]:

Do another write miss
PWriteMiss-MapHit-Victim(51275433)
Give the grant for the FlushBlock and then immediately after that for the RBRqst
Let the FBRply come here
And soon after the RBRply
Now read the word just written, and the other words from the block fetched
PReadHit[51275433]:
PReadHit[51275430]:
PReadHit[51275431]:
PReadHit[51275432]:
PReadHit[51275434]:
PReadHit[51275435]:
PReadHit[51275436]:
PReadHit[51275437]:
SmallCacheInner-IO:
Check the operation of each IO location in turn:
CWSOld:
Write CWSOld [01], Kernel Mode:
Read it back [01]:
Write CWSOld [01], User Mode:
Read it back [01]:
Write CWSOld [01], User Mode, ByteWrite:
Read it back [01]:
CWSNew:
Write CWSOld [03], Kernel Mode:
Read it back [03]:
Write CWSOld [03], User Mode:
Read it back [03]:
Write CWSOld [03], User Mode, ByteWrite:
Read it back [03]:
AID:
Write AID [09], Kernel Mode:
Read it back [09]:
Write AID [09], ByteWrite:
Read it back [09]:

Write AID [09], User Mode: Should generate protection fault
FaultCode:
Write FaultCode [0B], Kernel Mode:
Read it back [0B]:
Write FaultCode [0B], ByteWrite:
Read it back [0B]:

Write FaultCode [0B], User Mode: Should generate protection fault
InterruptStatus:
Write InterruptStatus [0D], Kernel Mode:
Read it back [0D]:
Write InterruptStatus [0D], ByteWrite:
Read it back [0D]:

Write InterruptStatus [0D], User Mode: Should generate protection fault
InterruptMask:
Write InterruptMask [0F], Kernel Mode:
Read it back [0F]:
Write InterruptMask [0F], ByteWrite:
Read it back [0F]:

Write InterruptMask [0F], User Mode: Should generate protection fault

Write 00 to InterruptMask [0F], Kernel Mode:
Read it back to check:

Write AA to InterruptMask [0F], Kernel Mode:
Read it back to check:

Write 00 to InterruptStatus [0D], Kernel Mode:
Read it back to check:
Starting at the highest order bit, set and then clear each bit, checking that SetReschedule is correctly generated. Since we wrote 1010 1010 (AA) into InterruptMask, we should get the alternating pattern 1010 1010 for SetReschedule.

Set bit 0:
Check that bit 0 got set:
Clear bit 0:
Check that bit 0 got cleared:
Set bit 1:
Set bit 3:
Check that bits 1+3 got set:
Clear bit 3:
Check that bit 3 got cleared:
Set bit 2:
Check that bit 2 got set:
Clear bit 1:
Clear bit 2:
Check that bits 1+2 got cleared:
Set bit 28:
Check that bit 28 got set:
Clear bit 28:
Check that bit 28 got cleared:
Set bit 29:
Check that bit 29 got set:
Clear bit 29:
Check that bit 29 got cleared:
Set bit 30:
Check that bit 30 got set:
Clear bit 30:
Check that bit 30 got cleared:
Set bit 31:
Check that bit 31 got set:
Clear bit 31:
Check that bit 31 got cleared:
Modes:
Write Modes [25], Kernel Mode:
Read it back [25]:
Write Modes [25], ByteWrite:
Read it back [25]:

Write Modes [25], User Mode: Should generate protection fault
LocalFaultCode:
Write LocalFaultCode [29], Kernel Mode:
Read it back [29]:
Write LocalFaultCode [29], ByteWrite:
Read it back [29]:

Write LocalFaultCode [29], User Mode: Should generate protection fault
SmallCacheInner-Misc:
Do a CWS[adrs=73FFAF00, oldVal=CC070504, newVal=DADADADA].  The current value of location 73FFAF00 is CC070504, so the CWS should succeed.  The CWS will be local since shared is not set.
Write CWSOld [01]:
Write CWSNew [03]:

Initiate CWS [73FFAF00, CC070504, DADADADA]:
Read location 73FFAF00 to make sure that it got written
Now do a CWS[adrs=73FFAF00, oldVal=CC070504, newVal=DADADADA].  The current value of location 73FFAF00 is DADADADA, so the CWS should fail.
Initiate CWS [73FFAF00, CC070504, DADADADA]:
Read location 73FFAF00 to make sure that it didn't get written
Next do a DeMap (Memory|Special|Write) to a page that has one entry in the cache (the one in line 1)
Initiate DeMap(Adrs=RA, Data=Don'tCare):
Here's the Demap request on our input wires, followed by the DeMapRply
Finally do a DeMap (Memory|Special|Write) to a page that has multiple entries in the cache (the one in Lines 0, 6 and 7)
Initiate DeMap(Adrs=RA, Data=Don'tCare):
Here's the Demap request on our input wires, followed by the DeMapRply
SmallCacheInner-ClrAllVPV:
Do a ClearAllVPV (Memory|Special|Write)
Initiate ClearAllVPV(Adrs=Don'tCare, Data=Don'tCare):
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