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0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 0 0 0 0 F 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 0 0 0 0 F 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 0 . –RamInterlockCtl.oracle Pradeep Sindhu September 24, 1987 12:07:17 pm PDT TEST COMPLETED March 3, 1987 1:51:35 pm PST [PSS] Changed to new naming convention and added xRSCmd April 3, 1987 9:26:11 pm PST [PSS] Checked again after putting together cache top level June 30, 1987 10:49:58 pm PDT [PSS] NB: Each line is one cycle The cache parameters assumed are: numBitsPerByte: 2, numBytesPerWord: 4, numCyclesPerLine: 4, numLines: 4 Reset Sequence: need to assert xWtMchVCam for one cycle to clear x's, but this will happen normally on first match Check that x's get flushed out in the right number of cycles: A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D B f a a W m B B B i a a l m C | R P A m o l a u o m m d d u u u t m m d a | R W B F g t s r D s s s m | L t u o a R B a R P A | a L s r R C t R W B | t a P Check PSide operation: Check Read; first directly from processor, then via PCtl: A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D B f a a W m B B B i a a l m C | R P A m o l a u o m m d d u u u t m m d a | R W B F g t s r D s s s m | L t u o a R B a R P A | a L s r R C t R W B | t a P PRead: WdAdrs = 0 PRead: WdAdrs = 1 PCtlRead: WdAdrs = 0 PCtlRead: WdAdrs = 1 Check Write; first directly from processor, then via PCtl. Simultaneously check the DrDBus lines: A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D B f a a W m B B B i a a l m C | R P A m o l a u o m m d d u u u t m m d a | R W B F g t s r D s s s m | L t u o a R B a R P A | a L s r R C t R W B | t a P PWrite: WdAdrs = 0 PWrite: WdAdrs = 1 PWrite: WdAdrs = 0, ByteSel=A PWrite: WdAdrs = 1, ByteSel=F PCtlWrite: WdAdrs = 0 PCtlWrite: WdAdrs = 1 PCtlWrite: WdAdrs = 0, ByteSel=0 PCtlWrite: WdAdrs = 1, ByteSel=4 Check BSide operation: Check Read A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D B f a a W m B B B i a a l m C | R P A m o l a u o m m d d u u u t m m d a | R W B F g t s r D s s s m | L t u o a R B a R P A | a L s r R C t R W B | t a P Block Read: Block Write: Word Write (word 0): Word Write (word 1): CWSRply match (word 0): CWSRply match (word 1): Check that interlock works: Fix a bus ram read and do processor accesses with various phase relationships: A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D B f a a W m B B B i a a l m C | R P A m o l a u o m m d d u u u t m m d a | R W B F g t s r D s s s m | L t u o a R B a R P A | a L s r R C t R W B | t a P PCycle0 leads ARM by 1 cycleno conflict: PCycle0 coincident with ARMno conflict: PCycle0 lags ARM by 1 cycleconflict, bus wins: PCycle0 lags ARM by 2 cyclesconflict, bus wins: PCycle0 lags ARM by 3 cyclesconflict, bus wins: PCycle0 lags ARM by 4 cyclesno conflict: Κ c˜šœ™Icode™1—J˜J™1J™TJ™XJ™J™J™J™J™™!J™GJ™—J™rJ™™>Jšœ&Οeœ™AJšœ&œ™AJšœ&œ™AJšœ%œ™@Jšœ%œ™@Jšœ%œ™>Jšœ%œ™:Jš œ"œœœœ ™5Jšœ!œ™3Jšœœ™+Jšœœ ™&Jšœœ ™%J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J˜J˜—™J™—™:Jšœ&œ™AJšœ&œ™AJšœ&œ™AJšœ%œ™@Jšœ%œ™@Jšœ%œ™>Jšœ%œ™:Jš œ"œœœœ ™5Jšœ!œ™3Jšœœ™+Jšœœ ™&Jšœœ ™%J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™—™bJšœ&œ™AJšœ&œ™AJšœ&œ™AJšœ%œ™@Jšœ%œ™@Jšœ%œ™>Jšœ%œ™:Jš œ"œœœœ ™5Jšœ!œ™3Jšœœ™+Jšœœ ™&Jšœœ ™%J™J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ™J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ™J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™ JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ™J™ JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J˜J˜J˜—™J™—™ Jšœ&œ™AJšœ&œ™AJšœ&œ™AJšœ%œ™@Jšœ%œ™@Jšœ%œ™>Jšœ%œ™:Jš œ"œœœœ ™5Jšœ!œ™3Jšœœ™+Jšœœ ™&Jšœœ ™%J™ JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™ JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J˜J˜J™J˜—™J™—™OJšœ&œ™AJšœ&œ™AJšœ&œ™AJšœ%œ™@Jšœ%œ™@Jšœ%œ™>Jšœ%œ™:Jš œ"œœœœ ™5Jšœ!œ™3Jšœœ™+Jšœœ ™&Jšœœ ™%J™)JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™(JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™/JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™0JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜J™0JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ™J™)JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ˜JšœA˜AJšœA˜AJ™J˜—J˜—…—;ΘZΑ