0 1 0 0 0 0 0 | x x x 0 0 1 0 0 0 0 0 | x x x 0 0 0 0 0 0 0 0 | x x 1 0 0 0 0 0 0 0 0 | x x 1 0 0 1 0 0 0 0 0 | x x 1 0 0 1 0 0 0 0 0 | x x 0 0 0 0 0 0 0 0 0 | x x 1 0 0 0 0 0 0 0 0 | x x 1 0 0 0 0 0 0 0 0 | x x 1 0 0 0 0 0 0 0 0 | x x 0 0 1 0 1 0 1 0 1 | 1 1 0 1 -- set them to 1 1 0 1 0 1 0 1 | 1 1 0 1 1 0 0 0 0 0 1 | 1 1 0 1 0 0 0 0 0 0 0 | 1 1 0 0 -- make sure the 1 stays latched even when the 1 0 0 1 0 1 0 | 1 1 0 1 1 0 0 1 0 1 0 | 1 1 0 1 1 0 1 0 1 0 0 | 1 1 0 1 -- set them back to 1 0 0 0 0 0 0 0 | 1 1 0 0 1 0 0 1 0 1 1 | 0 0 0 1 -- set them to 0 1 0 0 1 0 1 1 | 0 0 0 1 1 0 0 0 0 0 1 | 0 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 -- make sure the 0 stays latched even when the 1 0 1 0 1 0 0 | 0 0 0 1 1 0 1 0 1 0 0 | 0 0 0 1 1 0 0 1 0 1 0 | 0 0 0 1 -- set it back to 0 0 0 0 0 0 0 0 | 0 0 0 0 2 0 1 0 1 0 1 | 1 1 0 2 -- set it to a 1 2 0 1 0 1 0 1 | 1 1 0 2 2 0 0 0 0 0 1 | 1 1 0 2 0 0 0 0 0 0 0 | 1 1 0 0 2 0 0 1 0 1 1 | 0 0 0 2 -- set it to a 0 2 0 0 1 0 1 1 | 0 0 0 2 2 0 0 0 0 0 1 | 0 0 0 2 0 0 0 0 0 0 0 | 0 0 0 0 4 0 1 0 1 0 1 | 1 1 0 4 -- set it to a 1 4 0 1 0 1 0 1 | 1 1 0 4 4 0 0 0 0 0 1 | 1 1 0 4 0 0 0 0 0 0 0 | 1 1 0 0 4 0 0 1 0 1 1 | 0 0 0 4 -- set it to a 0 4 0 0 1 0 1 1 | 0 0 0 4 4 0 0 0 0 0 1 | 0 0 0 4 0 0 0 0 0 0 0 | 0 0 0 0 8 0 1 0 1 0 1 | 1 1 0 8 -- set it to a 1 8 0 1 0 1 0 1 | 1 1 0 8 8 0 0 0 0 0 1 | 1 1 0 8 0 0 0 0 0 0 0 | 1 1 0 0 8 0 0 1 0 1 1 | 0 0 0 8 -- set it to a 0 8 0 0 1 0 1 1 | 0 0 0 8 8 0 0 0 0 0 1 | 0 0 0 8 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 | 0 0 0 1 2 0 0 0 0 0 1 | 0 0 0 2 4 0 0 0 0 0 1 | 0 0 0 4 8 0 0 0 0 0 1 | 0 0 0 8 0 1 0 0 0 0 0 | 0 0 0 0 0 1 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 | 1 0 1 1 1 0 0 0 0 0 1 | 1 0 1 1 1 0 0 0 0 0 1 | 1 0 1 1 0 0 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 2 0 0 0 0 0 1 | 1 0 1 2 2 0 0 0 0 0 1 | 1 0 1 2 2 0 0 0 0 0 1 | 1 0 1 2 0 0 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 4 0 0 0 0 0 1 | 1 0 1 4 4 0 0 0 0 0 1 | 1 0 1 4 4 0 0 0 0 0 1 | 1 0 1 4 0 0 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 0 1 0 0 0 0 0 | 1 0 0 0 8 0 0 0 0 0 1 | 1 0 1 8 8 0 0 0 0 0 1 | 1 0 1 8 8 0 0 0 0 0 1 | 1 0 1 8 0 0 0 0 0 0 0 | 1 0 0 0 1 0 0 1 1 0 1 | 0 1 0 1 2 0 0 1 1 0 1 | 0 1 0 2 4 0 0 1 1 0 1 | 0 1 0 4 8 0 0 1 1 0 1 | 0 1 0 8 0 1 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 1 0 0 0 0 0 1 | 0 1 1 0 1 0 0 0 0 0 1 | 0 1 1 0 1 0 0 0 0 0 1 | 0 1 1 0 0 0 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 2 0 0 0 0 0 1 | 0 1 1 0 2 0 0 0 0 0 1 | 0 1 1 0 2 0 0 0 0 0 1 | 0 1 1 0 0 0 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 4 0 0 0 0 0 1 | 0 1 1 0 4 0 0 0 0 0 1 | 0 1 1 0 4 0 0 0 0 0 1 | 0 1 1 0 0 0 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 0 1 0 0 0 0 0 | 0 1 0 0 8 0 0 0 0 0 1 | 0 1 1 0 8 0 0 0 0 0 1 | 0 1 1 0 8 0 0 0 0 0 1 | 0 1 1 0 0 0 0 0 0 0 0 | 0 1 0 0 ˆSharedOwner.oracle Pradeep Sindhu March 17, 1987 7:08:21 pm PST TEST COMPLETED February 15, 1987 6:05:35 pm PST [PSS] Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file. Signal Order is: RamSelectIn CtlPWtInProg BCtlSetOw BCtlClrOw CtlSetSh CtlClrSh LdSORdLatch | ArrayOwOut ArrayShOut PWtInProg RamSelectOut PWtInProg: Check that X's get flushed out from PWtInProg. Also check the timing of the rising and falling edges for this signal: Shared and Owner bits in array and RdLatch in interface. Write a 1 and then a 0 into the shared and owner bits in each line and check that the values got written. Since PWtInProg is kept low, RamSelectIn=RamSelectOut, so we check RamSelectOut as well. Also, during the code for line 1 check that the RdLatch works. Line 1: -- array values are changed around -- array value is changed around Line 2: Line 3: Line 4: At this point all of the shared and owner bits should be 0. Check this. Check that a processor write sets owner for each line in turn. Line 1: Line 2: Line 3: Line 4: Finally, for each line check that if the shared bit is already set, then the owner bit does not get set from the processor side, and RamSelectOut stays 0. First clear all owner bits and set all shared bits to prepare for the check. Line 1: Line 2: Line 3: Line 4: . Κά˜šœ™Icode™,—J˜J™6J™J™…J™™JšœOΟeœ.™~—J™™€J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜J˜—™Ί™JšœΟc˜)J˜J˜J˜Jšœž.˜GJšœ.™.Jšœ˜Jšœ˜J˜Jšœž˜.J˜J˜Jšœž˜)J˜J˜J˜Jšœž.˜GJšœ,™,Jšœ˜Jšœ˜J˜Jšœž˜,J˜J˜—™Jšœž˜)J˜J˜J˜Jšœ˜J˜Jšœž˜)J˜J˜J˜Jšœ˜J˜—™Jšœž˜)J˜J˜J˜Jšœ˜J˜Jšœž˜)J˜J˜J˜Jšœ˜J˜—™Jšœž˜)J˜J˜J˜Jšœ˜J˜Jšœž˜)J˜J˜J˜Jšœ˜J˜——™GJšœ˜Jšœ˜Jšœ˜Jšœ˜J˜—J™™>™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J˜—J™™šJ™™LJšœ˜Jšœ˜Jšœ˜Jšœ˜J˜—™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J™™Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜J˜Jšœ˜Jšœ˜—J˜—J˜J™—…— <