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x x 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 ( 0 1 1 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 ( 0 1 1 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 4 0 0 1 0 0 0 0 0 1 0 1 0 1 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 4 4 0 0 1 0 0 0 0 0 0 0 1 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 4 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 ( 0 1 1 1 1 1 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 ( 0 1 1 1 1 1 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) C C 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) C C 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) C C 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 0 ) ( x x x x x x x x x ) x x x 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 1 1 0 0 ) ( x x x x x x x x x ) x x x 0 C 0 0 1 0 0 0 1 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 0 1 0 ) ( x x x x x x x x x ) x x x 0 C 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 0 1 0 ) ( x x x x x x x x x ) x x x 0 C 0 0 1 0 0 0 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 0 1 0 ) ( x x x x x x x x x ) x x x 0 C 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 0 1 1 ) ( 0 1 1 0 0 0 0 0 1 ) x x x 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 ( 0 0 0 0 0 0 0 0 0 ) | ( 0 1 0 1 ) ( 0 1 1 0 0 0 0 0 1 ) x x x 0 . ���t��RCam.oracle Paraminder Sahai July 21, 1987 11:01:32 am PDT Pradeep Sindhu January 2, 1988 12:49:48 pm PST TEST COMPLETED July 21, 1987 11:02:08 am PDT Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file. The Signal Order is: CamSelect Reset AVM AVct xCSCmdLo PCtlDrABusRB PCtlDrABusRP xRdRCam xPartRMch xDrRCamBL xLdRCamWR xEnCamSelExt BCycle1 RPValidIn RAdrsIn | RCamlfcCtlForFlags RAdrsOut LRM1ForVCam LRM1 ARM CamSelExt The Order for RCamlfcCtlForFlags is: Prech, nRCamLdRdLatch, RCamLdRdLatch, RCamDrRdLatch Do a Reset and wait for x's to get flushed out of the control part: Check that all the RPValid bits got cleared by the Reset: Line 0 Line 1 Line 2 Line 3 For each line write the number of that line and check that it got written; we need to do all the writes before any of the reads to avoid putting Rosemary into an infinite loop: Line 0: Write Line 1: Write Line 2: Write Line 3: Write Line 0: Read Line 1: Read Line 2: Read Line 3: Read Line 3 Write all ones Line 3 Read Read Line 2 and Line 3 with EnCamSelExt = 0 to check that the page part alone can be read (the block bits should read as 0 since the bit lines are precharged to 1, and we are reading from nBit and the valid bit should, of course, read as 1) Line 2 Read Line 3 Read Check Match circuitry (simultaneously check timing of QStage1): Check that RAdrsin = 0 causes line 0 to match. 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