0000 0 0 0 | xxxx xx x xx x xx AA81 0 0 0 | xxxx 00 x xx x 00 0004 0 0 0 | xxxx 01 x xx x 1F AA85 0 0 0 | xxxx 02 x xx x 00 0010 0 0 0 | xxxx 03 x xx x 1F AA91 0 0 0 | xxxx 04 x xx x 00 0011 0 0 0 | xxxx 05 x xx x 1F AA81 0 0 0 | xxxx xx x xx x xx -- Cycle# 0000 1 0 0 | xxxx 01 x xx x 1F -- (2) 0000 0 0 0 | xxxx 00 x 1F 0 00 -- (3) 0000 0 1 0 | xxxx 00 x 1F 0 00 -- (4) 0000 0 0 0 | xxxx 00 1 1F 0 00 -- (5) 0000 0 0 1 | xxxx 00 1 1F 0 00 -- (6) 0000 0 0 0 | AA81 00 1 1F 0 00 -- (7) 0000 0 0 0 | AA81 00 1 1F 0 00 -- (8) 0000 0 0 0 | AA81 00 1 1F 0 00 -- (9) AA1D 0 0 0 | AA81 00 1 1F 0 00 -- Cycle# 0000 1 0 0 | AA81 07 1 1F 0 1E -- (2) 0000 0 0 0 | AA81 00 1 1E 1 00 -- (3) 0000 0 1 0 | AA81 00 1 1E 1 00 -- (4) 0000 0 0 0 | AA81 00 7 1E 1 00 -- (5) 0000 0 0 1 | AA81 00 7 1E 1 00 -- (6) 0000 0 0 0 | AA1D 00 7 1E 1 00 -- (7) 0000 0 0 0 | AA1D 00 7 1E 1 00 -- (8) 0000 0 0 0 | AA1D 00 7 1E 1 00 -- (9) 0A19 0 0 0 | AA1D 00 7 1E 1 00 -- Cycle# 0000 1 0 0 | AA1D 05 7 1E 1 06 -- (2) AA81 0 0 0 | AA1D 00 7 06 1 00 -- (3) 0000 1 1 0 | AA1D 01 7 06 1 1F -- (4) AA1C 0 0 0 | AA1D 00 5 1F 0 00 -- (5) 0000 1 1 1 | AA1D 06 5 1F 0 1E -- (6) D555 0 0 0 | 0A19 00 1 1E 1 00 -- (7) 0000 1 1 1 | 0A19 FF 1 1E 1 10 -- (8) 0000 0 0 0 | AA81 00 6 10 0 00 -- (9) 0000 0 1 1 | AA81 00 6 10 0 00 -- (10) 0000 0 0 0 | AA1C 00 7 10 0 00 -- (11) 0000 0 0 1 | AA1C 00 7 10 0 00 -- (12) 0000 0 0 0 | D555 00 7 10 0 00 -- (13) 0000 0 0 0 | D555 00 7 10 0 00 -- (14) . ÚBCyclePipe.oracle Created: Pradeep Sindhu, October 4, 1987 5:51:03 pm PDT Pradeep Sindhu, October 5, 1987 1:18:57 pm PDT TEST COMPLETED: October 5, 1987 1:18:56 pm PDT NB: Each line corresponds to one cycle of the DynaBus clock. First check the first stage register using Adrs2 and BCmd2: D B B B | Q A B B R B 1 C C C | 7 d W C p C y y y | 8 r d m l m c c c | s A d y d l l l | 2 d 3 S 2 e e e | r 4 h 2 4 6 | s d | 5 3 6 4 Now check the second, third, and fourth stages: D B B B | Q A B B R B 1 C C C | 7 d W C p C y y y | 8 r d m l m c c c | s A d y d l l l | 2 d 3 S 2 e e e | r 4 h 2 4 6 | s d | 5 3 6 4 D B B B | Q A B B R B 1 C C C | 7 d W C p C y y y | 8 r d m l m c c c | s A d y d l l l | 2 d 3 S 2 e e e | r 4 h 2 4 6 | s d | 5 3 6 4 Now, put a different value every two cycles to simulate maximum rate D B B B | Q A B B R B 1 C C C | 7 d W C p C y y y | 8 r d m l m c c c | s A d y d l l l | 2 d 3 S 2 e e e | r 4 h 2 4 6 | s d | 5 3 6 4 ʘšœ™JšÏbœ0™7Jšœ.™.J™—J™.J™J™