[_CD4_]<dragon7.0>SmallCache>Oracle>RamInterlockCtl.oracle!2

RamInterlockCtl.oracle

Pradeep Sindhu September 24, 1987 12:07:17 pm PDT

TEST COMPLETED March 3, 1987 1:51:35 pm PST [PSS]

Changed to new naming convention and added xRSCmd April 3, 1987 9:26:11 pm PST [PSS]

Checked again after putting together cache top level June 30, 1987 10:49:58 pm PDT [PSS]

NB: Each line is one cycle

The cache parameters assumed are:

numBitsPerByte: 2, numBytesPerWord: 4, numCyclesPerLine: 4, numLines: 4

Reset Sequence: need to assert xWtMchVCam for one cycle to clear x's, but this will happen normally on first match

Check that x's get flushed out in the right number of cycles:

A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n

R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E

M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n

l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R

D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S

r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d

D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D

B f a a W m B B B i a a l m C | R P A m o l a

u o m m d d u u u t m m d a | R W B F g t

s r D s s s m | L t u o a

R B a R P A | a L s r

R C t R W B | t a P

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 x x x x x x x x x x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 x x x x x x x x x x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 x x x x x x x x x

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 x 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

Check PSide operation:

Check Read; first directly from processor, then via PCtl:

A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n

R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E

M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n

l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R

D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S

r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d

D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D

B f a a W m B B B i a a l m C | R P A m o l a

u o m m d d u u u t m m d a | R W B F g t

s r D s s s m | L t u o a

R B a R P A | a L s r

R C t R W B | t a P

PRead: WdAdrs = 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 1 | 0 0 0 1 1 0 0 0 x 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 0 0 | 0 0 0 1 1 0 0 1 x 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 0 0 | 0 0 0 1 1 0 0 1 x 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 | 0 0 0 1 1 0 0 0 x 0 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 | 0 0 0 1 1 0 0 0 x 0 1 0 0

PRead: WdAdrs = 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 | 0 0 0 1 1 0 0 0 x 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 | 0 0 0 1 1 0 0 0 x 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 1 0 0 | 0 0 0 1 1 0 0 1 x 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 1 0 0 | 0 0 0 1 1 0 0 1 x 1 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 | 0 0 0 1 1 0 0 0 x 1 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 | 0 0 0 1 1 0 0 0 x 1 1 0 0

PCtlRead: WdAdrs = 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 1 | 0 0 0 1 1 0 0 0 x 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 1 | 0 0 0 1 1 0 0 0 x 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 0 0 0 | 0 0 0 1 1 0 0 1 x 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0 0 0 | 0 0 0 1 1 0 0 0 x 0 1 0 0

PCtlRead: WdAdrs = 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 | 0 0 0 1 1 0 0 0 x 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 1 | 0 0 0 1 1 0 0 0 x 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x 1 0 0 | 0 0 0 1 1 0 0 1 x 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 0 0 | 0 0 0 1 1 0 0 0 x 1 1 0 0

Check Write; first directly from processor, then via PCtl. Simultaneously check the DrDBus lines:

A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n

R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E

M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n

l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R

D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S

r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d

D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D

B f a a W m B B B i a a l m C | R P A m o l a

u o m m d d u u u t m m d a | R W B F g t

s r D s s s m | L t u o a

R B a R P A | a L s r

R C t R W B | t a P

PWrite: WdAdrs = 0

0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 F 0 3 1 | 1 1 1 1 1 0 0 0 F 1 1 0 0

0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 F 0 3 1 | 1 1 1 1 1 0 0 0 F 1 1 3 1

0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 F 0 3 0 | 1 1 0 1 1 1 1 0 F 0 1 3 1

0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 F 0 3 0 | 1 1 0 1 1 1 1 0 F 0 1 2 1

0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 F 0 3 0 | 1 0 1 1 1 0 0 0 F 0 1 2 0

0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 F 0 3 0 | 1 0 1 1 1 0 0 0 F 0 1 3 0

PWrite: WdAdrs = 1

0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 F 1 2 1 | 1 0 0 1 1 0 0 0 F 0 1 3 0

0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 F 1 2 1 | 1 0 0 1 1 0 0 0 F 0 1 2 1

0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 F 1 2 0 | 0 1 1 1 1 1 1 0 F 1 1 2 1

0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 F 1 2 0 | 0 1 0 1 1 0 0 0 F 1 1 2 0

PWrite: WdAdrs = 0, ByteSel=A

0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 A 0 1 1 | 0 0 1 1 1 0 0 0 A 1 1 2 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 A 0 1 1 | 0 0 1 1 1 0 0 0 A 1 1 1 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 1 0 | 0 0 0 1 1 1 1 0 A 0 1 1 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 1 0 | 0 0 0 1 1 1 1 0 A 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 A 0 1 0 | 0 0 0 1 1 0 0 0 A 0 1 2 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 A 0 1 0 | 0 0 0 1 1 0 0 0 A 0 1 1 0

PWrite: WdAdrs = 1, ByteSel=F

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 F 1 0 1 | 0 0 0 1 1 0 0 0 F 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 F 1 0 1 | 0 0 0 1 1 0 0 0 F 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 F 1 0 0 | 0 0 0 1 1 1 1 0 F 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 F 1 0 0 | 0 0 0 1 1 1 1 0 F 1 1 2 1

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 F 1 0 0 | 0 0 0 1 1 0 0 0 F 1 1 2 0

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 F 1 0 0 | 0 0 0 1 1 0 0 0 F 1 1 0 0

PCtlWrite: WdAdrs = 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 1 | 0 0 0 1 1 0 0 0 3 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 1 | 0 0 0 1 1 0 0 0 3 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 2 0 | 0 0 0 1 1 1 1 0 3 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 2 0 | 0 0 0 1 1 1 1 0 3 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 | 0 0 0 1 1 0 0 0 3 0 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 | 0 0 0 1 1 0 0 0 3 0 1 0 0

PCtlWrite: WdAdrs = 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 | 0 0 0 1 1 0 0 0 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 | 0 0 0 1 1 0 0 0 1 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 2 0 | 0 0 0 1 1 1 1 0 1 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 2 0 | 0 0 0 1 1 1 1 0 1 1 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 | 0 0 0 1 1 0 0 0 1 1 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 | 0 0 0 1 1 0 0 0 1 1 1 0 0

PCtlWrite: WdAdrs = 0, ByteSel=0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 1 0 0 0 0 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 | 0 0 0 1 1 1 1 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 | 0 0 0 1 1 1 1 0 0 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 0

PCtlWrite: WdAdrs = 1, ByteSel=4

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 0 1 | 0 0 0 1 1 0 0 0 4 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 0 1 | 0 0 0 1 1 0 0 0 4 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 2 0 | 0 0 0 1 1 1 1 0 4 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 4 1 2 0 | 0 0 0 1 1 1 1 0 4 1 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 0 0 | 0 0 0 1 1 0 0 0 4 1 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 1 0 0 | 0 0 0 1 1 0 0 0 4 1 1 0 0

Check BSide operation:

Check Read

A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n

R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E

M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n

l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R

D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S

r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d

D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D

B f a a W m B B B i a a l m C | R P A m o l a

u o m m d d u u u t m m d a | R W B F g t

s r D s s s m | L t u o a

R B a R P A | a L s r

R C t R W B | t a P

Block Read:

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 3 1

0 0 0 0 1 0 0 3 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 3 1

0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 3 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

Block Write:

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 F 0 0 1 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

Word Write (word 0):

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 F 0 1 1 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

Word Write (word 1):

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 F 1 1 1 1

0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 1 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

CWSRply match (word 0):

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 F 0 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

CWSRply match (word 1):

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 1 0 1 1

0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 1 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 F 0 1 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 1 1 0 1

Check that interlock works:

Fix a bus ram read and do processor accesses with various phase relationships:

A B B B B B B B P P P P P P P P P P x | x x x E R P x x x x x x n

R C C C C W C C C C C C C C C B W C W | D D D a a W W R B W S R E

M t t t t d t t t t t m y t t y d t t | r r r r m t t d y d e S n

l l l l A l l l l l d c l l t A l M | D D D l F I R R t A l C R

D R W R d S R D D D W l W R e d R c | B B B y o n a a e d W m S

r a t d r e S r r r t e t d S r S h | u u u R r P m m S r d d

D m R R s l C D D D B 0 R R e s C V | s s s a P r e s D

B f a a W m B B B i a a l m C | R P A m o l a

u o m m d d u u u t m m d a | R W B F g t

s r D s s s m | L t u o a

R B a R P A | a L s r

R C t R W B | t a P

PCycle0 leads ARM by 1 cycle—no conflict:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 1 0 0 0 0 1 1 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 2 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 2 0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

PCycle0 coincident with ARM—no conflict:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 1 0 0 0 0 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 0 1 1 1 0 A 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 0 1 1 1 0 A 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 0

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

PCycle0 lags ARM by 1 cycle—conflict, bus wins:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 1 0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

PCycle0 lags ARM by 2 cycles—conflict, bus wins:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

PCycle0 lags ARM by 3 cycles—conflict, bus wins:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

PCycle0 lags ARM by 4 cycles—no conflict:

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 F 0 0 1 1

0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 1 F 0 0 1 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 1 0 0 0 0 F 0 0 1 0

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 A 0 0 0 | 0 0 0 1 1 1 1 0 A 0 1 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 2 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 1 1 0 0 0 0 0 1 0 0

.