[_CD4_]<dragon7.0>SmallCache>Oracle>RCamLine.oracle!1

RCamLine.oracle

Pradeep Sindhu March 17, 1987 7:10:46 pm PST

TEST COMPLETED February 23, 1987 1:23:49 pm PST [PSS]

Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file.

The cache parameters assumed are:

numBitsPerByte: 2, numBytesPerWord: 4, numCyclesPerLine: 1, numLines: 4

Do a Reset and wait for x's to get flushed out of the control part:

A R R P W E B R R R R R R Q L L A

c e d a t n C P B P P B P S R R R

c s R r M C y V l a V l a t m M M

e e c t c a c a o g a o g a 1 1

s t a R h m l l c e l c e g F

s m m R S e i k I i k O e o

c c e 1 d I n d O u 1 r

0 1 0 0 0 0 0 0 0 00 | x x xx x x x x -- (2)

0 1 0 0 0 0 0 0 0 00 | x x xx x x x x

0 0 0 0 0 0 0 0 0 00 | x x xx 0 x x x

For each line write the number of that line and check it got written:

Signals

A R R P W E B R R R R R R Q L L A

c e d a t n C P B P P B P S R R R

c s R r M C y V l a V l a t m M M

e e c t c a c a o g a o g a 1 1

s t a R h m l l c e l c e g F

s m m R S e i k I i k O e o

c c e 1 d I n d O u 1 r

Line 0: Write

0 0 0 0 1 0 0 1 3 00 | x x xx x x x x

0 0 0 0 0 0 0 1 3 00 | x x xx x x x x

1 0 0 0 0 1 0 1 3 00 | x x xx x x x x

1 0 0 0 0 1 0 0 0 00 | x x xx x x x x

0 0 0 0 0 0 0 0 0 00 | x x xx x x x x

Line 0: Read

0 0 1 0 0 0 0 0 0 00 | x x xx x x x x

0 0 1 0 0 1 0 0 0 00 | x x xx x x x x

1 0 1 0 0 1 0 0 0 00 | x 3 xx x x x x

1 0 0 0 0 1 0 0 0 00 | x 3 xx x x x x

0 0 0 0 0 0 0 0 0 00 | x 3 xx x x x x

Line 0: Write

0 0 0 0 1 0 0 1 1 00 | x 3 xx x x x x

0 0 0 0 0 0 0 1 1 00 | x 3 xx x x x x

1 0 0 0 0 1 0 1 1 00 | x 3 xx x x x x

1 0 0 0 0 1 0 0 0 00 | x 3 xx x x x x

0 0 0 0 0 0 0 0 0 00 | x 3 xx x x x x

Line 0: Read

0 0 1 0 0 0 0 0 0 00 | x 3 xx x x x x

0 0 1 0 0 1 0 0 0 00 | x 3 xx x x x x

1 0 1 0 0 1 0 0 0 00 | x 1 xx x x x x

1 0 0 0 0 1 0 0 0 00 | x 1 xx x x x x

0 0 0 0 0 0 0 0 0 00 | x 1 xx x x x x

.