[_CD4_]<dragon7.0>SmallCache>Oracle>RCamInterlockCtl.oracle!2

RCamInterlockCtl.oracle

Pradeep Sindhu November 10, 1987 1:32:08 am PST

TEST COMPLETED March 3, 1987 6:20:20 pm PST [PSS]

Revised and retested April 15, 1987 10:18:51 am PDT

Checked again after putting together cache top level June 30, 1987 11:15:43 pm PDT [PSS]

Checked after moving stuff from array interface controls November 9, 1987 6:46:21 pm PST [PSS]

NB: Each line is one cycle

Reset Sequence: x's get flushed out by BCycle0 and friends

Check that x's get flushed out in the right number of cycles, and that LdRML1 and ClampRM are generated correctly during Reset:

R x P F B B B B B B M M D A P P P P | R x x x x x x x R x L

e W C o C C C C C C y y e R C C C C | P E C R L D E P C L d

s t t r t y y y y y R M M M t t t t | V n S d d r n a a d R

e M l c l c c c c c B a a l l l l | a C C R R R C r m U M

t c P e R l l l l l R p p E C R E | l a m C C C a t F s L

h a I P e e e e e p R R n S d n | i m d a a a m R o e 1

V r O V 0 1 2 3 4 l p p C C R R | d S m m m S M r

C t M a y l l a m C C | e W B e c P

a V i l y y m d a a | l R L l h

m M s i 1 1 S m m | E

c m d e S | x

h a l e | t

t E l |

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 x x 0 x 0 x 0 1 x x

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 x x 0 x 0 x 0 1 x 1

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 x x 0 1 0 0 0 1 0 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 x x 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 x 0 0 0 0 0 0 0 0

0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 | 1 0 x 0 1 1 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 1 0 x 0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 1 0 x 0 0 0 0 0 0 0 1

0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 | 1 0 x 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

Check PSide Signals:

R x P F B B B B B B M M D A P P P P | R x x x x x x x R x L

e W C o C C C C C C y y e R C C C C | P E C R L D E P C L d

s t t r t y y y y y R M M M t t t t | V n S d d r n a a d R

e M l c l c c c c c B a a l l l l | a C C R R R C r m U M

t c P e R l l l l l R p p E C R E | l a m C C C a t F s L

h a I P e e e e e p R R n S d n | i m d a a a m R o e 1

V r O V 0 1 2 3 4 l p p C C R R | d S m m m S M r

C t M a y l l a m C C | e W B e c P

a V i l y y m d a a | l R L l h

m M s i 1 1 S m m | E

c m d e S | x

h a l e | t

t E l |

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 1 0 0

0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 | 0 0 0 1 0 0 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 | 0 0 2 0 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 | 0 0 3 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 0 0 0 0 0 0 1 0 0

Check BSide Signals:

R x P F B B B B B B M M D A P P P P | R x x x x x x x R x L

e W C o C C C C C C y y e R C C C C | P E C R L D E P C L d

s t t r t y y y y y R M M M t t t t | V n S d d r n a a d R

e M l c l c c c c c B a a l l l l | a C C R R R C r m U M

t c P e R l l l l l R p p E C R E | l a m C C C a t F s L

h a I P e e e e e p R R n S d n | i m d a a a m R o e 1

V r O V 0 1 2 3 4 l p p C C R R | d S m m m S M r

C t M a y l l a m C C | e W B e c P

a V i l y y m d a a | l R L l h

m M s i 1 1 S m m | E

c m d e S | x

h a l e | t

t E l |

Other than MyRBRply and DeMapRply

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

MyRBRply with ARM

0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 3 0 0 0 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 3 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 0 0 0 0 0 0 1 0 0

MyRBRply no ARM

0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 1 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 1 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 1 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 1 0 0 0 0 0 0 1 0 0

DeMapRply

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 | 0 0 0 0 1 1 0 1 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

MyMapRply1

0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 | 0 0 0 1 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 0