PInterfaceCtl.oracle
Pradeep Sindhu July 1, 1987 5:57:50 pm PDT
TEST COMPLETED March 10, 1987 1:32:33 pm PST [PSS]
Tested updated PInterfaceCtl March 19, 1987 4:52:59 pm PST
Retested after completing top level of cache July 1, 1987 5:57:45 pm PDT [PSS]
NB: Each line corresponds to one cycle of the DynaBus clock
Reset Sequence:
8 cycles of Reset
Do a Reset and check that x's get flushed out in the right number of cycles; note that Reset must be held high as long as we haven't flushed out x's from PCycle2; also check DrPAdrs at the same time (Nor2[ABusCmd[0], ABusCmd[1]):
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
 
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 x x x 0 x x 0 x 1 0 -- PhA
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 x x 0 x x 0 x 1 0
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 x 0 x 0 x x 1 0 -- PhB
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 0 x 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 x 0 1 1 0 -- PhA
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 x 0 1 1 0
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 0 x 1 1 0 -- PhB
0 0 0 0 0 0 0 0 0 0 0 1 | 0 0 0 0 0 0 0 0 0 x 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0
Do different operations and check outputs:
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
 
First do a PRead hit. PCycle0, 1 and 2 should each be one cycle long and follow each other:
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 1 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
8 0 1 1 0 0 1 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 1 1 0
Do a PWrite hit. PCycle0, 1 and 2 should each be one cycle long:
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 0 1 0 0 0 0 1 0 1 1 0
9 1 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
9 0 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 0 1 1 1 0 1 1 1 0 
Then do a PWrite to shared data; try several phasings of PCtlReleaseP. PCycle0, 1 and 2 should each be one cycle long. Reject should get asserted during PCycle2, then deasserted during the next PhB:
PCtlReleaseP in PhA.1
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 0 1 0 0 0 0 1 0 1 1 0
9 1 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
9 0 1 1 0 0 1 1 0 0 0 0 | 1 0 0 0 0 1 1 1 0 1 0 1 0 
9 0 1 1 0 0 0 1 1 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhA.2
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 0 1 0 0 0 0 1 0 1 1 0
9 1 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
9 0 1 1 0 0 1 1 0 0 0 0 | 1 0 0 0 0 1 1 1 0 1 0 1 0 
9 0 1 1 0 0 0 1 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
9 0 1 1 0 0 0 0 1 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhB.1
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 0 1 0 0 0 0 1 0 1 1 0
9 1 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
9 0 1 1 0 0 1 1 0 0 0 0 | 1 0 0 0 0 1 1 1 0 1 0 1 0 
9 0 1 1 0 0 0 1 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0
9 0 1 1 0 0 0 0 1 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhB.2
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
9 1 1 1 0 0 0 0 0 0 0 0 | 1 0 0 1 0 0 0 0 1 0 1 1 0
9 1 1 1 0 0 1 0 0 0 0 0 | 1 0 0 0 1 0 1 0 0 1 1 1 0 -- PhB
9 0 1 1 0 0 1 1 0 0 0 0 | 1 0 0 0 0 1 1 1 0 1 0 1 0 
9 0 1 1 0 0 0 1 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 0 0 0 0 1 1 0
9 0 1 1 0 0 0 0 0 0 0 0 | 1 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
9 0 1 1 0 0 0 0 1 0 0 0 | 1 0 0 0 0 0 1 0 0 0 1 1 0
Do a PRead miss. Reject should be asserted during PCycle1; try different phasings of PCtlReleaseP:
PCtlReleaseP in PhA.1
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 1 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhA.2
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 1 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhB.1
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 1 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP in PhB.2
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
8 0 1 1 0 0 0 0 1 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
Do a PBIOWrite. Reject should be asserted during PCycle1:
F 1 1 1 0 0 0 0 0 0 0 0 | 1 1 1 0 0 0 0 0 1 0 1 1 0 -- PhA
F 1 1 1 0 0 0 0 0 0 0 0 | 1 1 0 1 0 0 0 0 1 0 1 1 0
F 1 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 1 0 1 0 0 1 0 1 0 -- PhB
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 1 1 1 0 1 0 1 0 
F 0 1 1 0 0 0 0 1 0 0 0 | 1 1 0 0 0 0 0 0 0 0 1 1 0 -- PhA
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 0 0 0 0 1 1 0
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0 0 0 1 0 -- PhB
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0 0 0 1 0 
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 0 0 0 0 1 1 0 -- PhA
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 0 0 0 0 1 1 0
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0 0 1 1 0 -- PhB
F 0 1 1 0 0 0 0 0 0 0 0 | 1 1 0 0 0 0 1 0 0 0 1 1 0 
Do a PSpclRead. Reject should be asserted during PCycle1:
A 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
A 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
A 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
A 0 1 1 0 0 0 0 1 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
A 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
A 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
A 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
A 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 
Do a PRead with the Ram busy. Reject should be asserted during PCycle0, and PCycle0 should get stretched out for as many cycles as the Ram is busy:
8 1 0 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 0 0 0 0 0 0 0 0 0 0 | 0 0 1 1 0 0 0 0 1 0 1 1 0
8 1 0 0 0 0 0 0 0 0 0 0 | 0 0 1 1 0 0 1 0 0 1 0 1 0 -- PhB
8 0 1 0 0 0 0 0 0 0 0 0 | 0 0 1 1 0 0 1 0 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 1 0 1 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 1 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
Do a PSpclRead, then let processor proceed while keeping PCtlBusy asserted. Then do another PRead to see that Reject gets asserted during PCycle0 and then deasserted when PCtlBusy is deasserted:
A 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
A 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
A 1 1 1 1 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
A 0 1 1 1 0 0 0 1 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
A 0 1 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
A 0 1 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
A 0 1 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
A 0 1 1 1 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
8 1 1 1 1 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 1 0 0 0 0 0 0 0 | 0 0 1 1 0 0 0 0 1 0 1 1 0
8 1 1 1 1 0 0 0 0 0 0 0 | 0 0 1 1 0 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 1 1 0 0 1 0 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 1 0 1 0 0 0 | 0 0 0 0 1 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 1 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
Do a PRead that gets a fault. Ie. no ArrayVM, then PCtlReleaseP along with PCtlFault; try all possible phasings of PCtlReleaseP and PCtlFault relative to PhA, PhB:
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
PCtlReleaseP and PCtlFault in PhA.1
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 1 1 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP and PCtlFault in PhA.2
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 1 1 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP and PCtlFault in PhB.1
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 1 1 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
PCtlReleaseP and PCtlFault in PhB.2
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 1 0 0 0 0 0 1 0 1 1 0 -- PhA
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 1 0 0 0 0 1 0 1 1 0
8 1 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 1 0 1 0 0 1 0 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 1 1 1 0 1 0 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 0 1 0 -- PhB
8 0 1 1 0 0 0 0 1 1 0 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 -- PhA
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 0 1 1 0 
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0 -- PhB
8 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 1 0 0 0 1 1 0
Finally, check that Reschedule works:
P P E R P B A A P P S R | P P P P P P D L L L n n R
C C a a C c r r C C e e | C B C C C C r d d d R F e
m m r m t y r r t t t s | m I y y y y P P P P e a s
d d l F l c a a l l R e | d O c c c c B R A W j u c
 I y o B l y y R F e t | W W l l l l u d d t e l h
 n R r u e V S e a s  | t r e e e e s L r L c t e 
 C a P s 1 M h l u c  | B i - 0 1 2  a s a t B d
 S m  y   O e l h  | i t 1     t  t B  u
 B F     u a t e  | t e      c  c   l
 i o     t s  d  |        h  h   e
 t r      e  u  |     
  P      P  l  |     
SetReschedule during PhA.1
0 0 1 1 0 0 0 0 0 0 1 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1 
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 
SetReschedule during PhA.2
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 1 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0
SetReschedule during PhB.1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 1 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1
SetReschedule during PhB.2
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 1 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0 -- PhA
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 1 0 1 1 0
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0 -- PhB
0 0 1 1 0 0 0 0 0 0 0 0 | 0 0 0 0 0 0 0 0 0 1 1 1 0
 
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