CSMux.oracle
Pradeep Sindhu September 22, 1987 2:30:00 am PDT
Paraminder Sahai June 29, 1987 7:07:07 pm PDT
TEST COMPLETED February 13, 1987 [PSS]
Checked again after putting together cache top level June 30, 1987 2:46:51 pm PDT [PSS]
Note that clock supplied to circuit is half the speed of the oracle clock, so that one "cycle" corresponds to two lines in this file.
Signal Order is:
Victim LVM LRM (CSCmd) EnCamSel | ((nDecodedCmd) (DecodedCmd) EnOut) MuxOut
First, check that X's get flushed out naturally, and that the Cmd decoder works:
3 2 1 ( 0 0 ) 1 | ( ( x 1 1 1 ) ( 1 0 0 0 ) x ) x
3 2 1 ( 0 1 ) 1 | ( ( x 0 1 1 ) ( 0 1 0 0 ) x ) x
3 2 1 ( 1 0 ) 0 | ( ( x 1 0 1 ) ( 0 0 1 0 ) x ) x
3 2 1 ( 1 1 ) 0 | ( ( x 1 1 0 ) ( 0 0 0 1 ) 1 ) 3
3 2 1 ( 1 1 ) 0 | ( ( x 1 1 0 ) ( 0 0 0 1 ) 1 ) 3
3 2 1 ( 1 1 ) 0 | ( ( x 1 1 0 ) ( 0 0 0 1 ) 0 ) 0
Next, check that the right values appear at the output for different inputs
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 1
3 2 1 ( 1 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 2
3 2 1 ( 1 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 3
A B C ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 0
A B C ( 0 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) C
A B C ( 1 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) B
A B C ( 1 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) A
F A B ( 1 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) F
A F B ( 1 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) F
A B F ( 0 1 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) F
Then check the timing of the negative and positive going edges of EnOut
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 1 ) 0
3 2 1 ( 0 0 ) 0 | ( ( x x x x ) ( x x x x ) 0 ) 0
Finally, check that EnOut sets MuxOut to 0 when not asserted
3 2 1 ( 0 1 ) 0 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 1 0 ) 0 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 1 1 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
3 2 1 ( 0 0 ) 1 | ( ( x x x x ) ( x x x x ) 0 ) 0
.