BlockAssemblyRegister.oracle
Created: Pradeep Sindhu, October 4, 1987 5:51:03 pm PDT
Pradeep Sindhu, October 5, 1987 6:16:15 pm PDT
TEST COMPLETED: October 5, 1987 6:16:12 pm PDT
NB: Each line corresponds to one cycle of the DynaBus clock.
First check the first stage register using Adrs2 and BCmd2:
Put a sequence of 5 cycle packets with addresses 0, 2, 4, 6, ... to try different cyclic orders
C  B B B | B
y  C C C | l
c  y y t | k
l  c c l | W
e  l l B | t
I  e e l | D
n  0 1 k | a
    W | t 
    t | a      
    5 |       
0000 1 0 0 | xxxxxxxxxxxxxxxx
0080 0 1 0 | xxxxxxxxxxxxxxxx  -- Hdr Cycle (Cmd=1, Adrs=0)
0000 0 0 0 | xxxxxxxxxxxxxxxx  -- D0 Cycle
1111 0 0 0 | xxxxxxxxxxxxxxxx  -- D1 Cycle
2222 0 0 0 | xxxxxxxxxxxxxxxx  -- D2 Cycle
3333 1 0 1 | xxxxxxxxxxxxxxxx  -- D3 Cycle
0084 0 1 0 | 001B001B001B001B  -- Hdr Cycle (Cmd=1, Adrs=2)
0000 0 0 0 | 001B001B001B001B  -- D0 Cycle
1111 0 0 0 | xxxxxxxxxxxxxxxx  -- D1 Cycle
2222 0 0 0 | xxxxxxxxxxxxxxxx  -- D2 Cycle
3333 1 0 1 | xxxxxxxxxxxxxxxx  -- D3 Cycle
0090 0 1 0 | 00C600C600C600C6  -- Hdr Cycle (Cmd=1, Adrs=4)
0000 0 0 0 | 00C600C600C600C6  -- D0 Cycle
1111 0 0 0 | xxxxxxxxxxxxxxxx  -- D1 Cycle
2222 0 0 0 | xxxxxxxxxxxxxxxx  -- D2 Cycle
3333 1 0 1 | xxxxxxxxxxxxxxxx  -- D3 Cycle
0094 0 1 0 | 00B100B100B100B1  -- Hdr Cycle (Cmd=1, Adrs=6)
0000 0 0 0 | 00B100B100B100B1  -- D0 Cycle
1111 0 0 0 | xxxxxxxxxxxxxxxx  -- D1 Cycle
2222 0 0 0 | xxxxxxxxxxxxxxxx  -- D2 Cycle
3333 0 0 1 | xxxxxxxxxxxxxxxx  -- D3 Cycle
0000 0 0 0 | 006C006C006C006C
0000 0 0 0 | 006C006C006C006C
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