BWdWtPipe.oracle
Created: Pradeep Sindhu, October 4, 1987 5:51:03 pm PDT
Pradeep Sindhu, October 5, 1987 6:33:22 pm PDT
TEST COMPLETED: October 5, 1987 6:33:21 pm PDT
NB: Each line corresponds to one cycle of the DynaBus clock.
First check the first stage register using Adrs2 and BCmd2:
D E | Q Q
n | 2 6
B | 3 7
W |
d |
W |
t |
P |
i |
00 0 | xx xx -- Cycle 0
AA 1 | xx xx -- Cycle 1
00 0 | AA xx -- Cycle 2
01 1 | AA xx -- Cycle 3
00 0 | 01 xx -- Cycle 4
02 1 | 01 xx -- Cycle 5
00 0 | 02 AA -- Cycle 6
03 1 | 02 AA -- Cycle 7
00 0 | 03 01
10 1 | 03 01
00 0 | 10 02
20 1 | 10 02
00 0 | 20 03
FF 1 | 20 03
00 0 | FF 10
EE 1 | FF 10
00 0 | EE 20
BB 1 | EE 20
BB 0 | BB FF
BB 0 | BB FF
BB 0 | BB EE
BB 0 | BB EE
BB 0 | BB BB
BB 0 | BB BB
BB 0 | BB BB
BB 0 | BB BB
BB 0 | BB BB
.